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Results 1 - 10 of 15 for teq (0.02 sec)
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src/math/big/arith_arm.s
SBC.S $0, R5 MOVW.P R5, 4(R1) E4: TEQ R1, R4 BNE L4 MOVW $0, R0 MOVW.CC $1, R0 MOVW R0, c+28(FP) RET // func shlVU(z, x []Word, s uint) (c Word) TEXT ·shlVU(SB),NOSPLIT,$0 MOVW z_len+4(FP), R5 TEQ $0, R5 BEQ X7 MOVW z+0(FP), R1 MOVW x+12(FP), R2 ADD R5<<2, R2, R2 ADD R5<<2, R1, R5 MOVW s+24(FP), R3 TEQ $0, R3 // shift 0 is special BEQ Y7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 4K bytes - Viewed (0) -
test/codegen/condmove.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Oct 06 20:57:33 UTC 2023 - 6.2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc2.s
MOVV $4097, R4 // 2400001484048003 AND $-1, R4, R5 // 1efcbf0285f81400 AND $-1, R4 // 1efcbf0284f81400 MOVW $-1, F4 // 1efcbf02c4a71401 MOVW $1, F4 // 1e048002c4a71401 TEQ $4, R4, R5 // 8508005c04002a00 TEQ $4, R4 // 0408005c04002a00 TNE $4, R4, R5 // 8508005804002a00 TNE $4, R4 // 0408005804002a00 ADD $65536, R4, R5 // 1e02001485781000 ADD $4096, R4, R5 // 3e00001485781000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 10 15:50:11 UTC 2023 - 3K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/crypto/internal/bigmod/nat_arm.s
ADD R5<<2, R1, R5 MOVW $0, R4 B E9 L9: MOVW.P 4(R2), R6 MULLU R6, R3, (R7, R6) ADD.S R4, R6 ADC R0, R7 MOVW 0(R1), R4 ADD.S R4, R6 ADC R0, R7 MOVW.P R6, 4(R1) MOVW R7, R4 E9: TEQ R1, R5 BNE L9 MOVW R4, c+12(FP)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 22:37:58 UTC 2023 - 900 bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "TSTconst", argLength: 1, reg: gp1flags, asm: "TST", aux: "Int32", typ: "Flags"}, // arg0 & auxInt compare to 0 {name: "TEQ", argLength: 2, reg: gp2flags, asm: "TEQ", typ: "Flags", commutative: true}, // arg0 ^ arg1 compare to 0 {name: "TEQconst", argLength: 1, reg: gp1flags, asm: "TEQ", aux: "Int32", typ: "Flags"}, // arg0 ^ auxInt compare to 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// CMOVN R1, R2, R3 CMOVZ R1, R2, R3 // // conditional move on fp false/true // CMOVF R1, R2 CMOVT R1, R2 // // conditional traps // TEQ $1, R1, R2 TEQ $1, R1 // // other // CLO R1, R2 SQRTD F0, F1 MUL R1, R2, R3 // // RET // // LRETRN comma // asm doesn't support the trailing comma. // {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(TST x (SRL y z)) => (TSTshiftRLreg x y z) (TST x (SRA y z)) => (TSTshiftRAreg x y z) (TEQ x (SLLconst [c] y)) => (TEQshiftLL x y [c]) (TEQ x (SRLconst [c] y)) => (TEQshiftRL x y [c]) (TEQ x (SRAconst [c] y)) => (TEQshiftRA x y [c]) (TEQ x (SLL y z)) => (TEQshiftLLreg x y z) (TEQ x (SRL y z)) => (TEQshiftRLreg x y z) (TEQ x (SRA y z)) => (TEQshiftRAreg x y z) (CMN x (SLLconst [c] y)) => (CMNshiftLL x y [c])
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0)