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Results 1 - 4 of 4 for TEQconst (0.16 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (TSTshiftRA (MOVWconst [c]) x [d]) => (TSTconst [c] (SRAconst <x.Type> x [d]))
    (TEQshiftLL (MOVWconst [c]) x [d]) => (TEQconst [c] (SLLconst <x.Type> x [d]))
    (TEQshiftRL (MOVWconst [c]) x [d]) => (TEQconst [c] (SRLconst <x.Type> x [d]))
    (TEQshiftRA (MOVWconst [c]) x [d]) => (TEQconst [c] (SRAconst <x.Type> x [d]))
    (CMNshiftLL (MOVWconst [c]) x [d]) => (CMNconst [c] (SLLconst <x.Type> x [d]))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/rewriteARM.go

    		v.AddArg2(x, y)
    		return true
    	}
    	return false
    }
    func rewriteValueARM_OpARMTEQ(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (TEQ x (MOVWconst [c]))
    	// result: (TEQconst [c] x)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			x := v_0
    			if v_1.Op != OpARMMOVWconst {
    				continue
    			}
    			c := auxIntToInt32(v_1.AuxInt)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 486.8K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/ARMOps.go

    		{name: "TEQ", argLength: 2, reg: gp2flags, asm: "TEQ", typ: "Flags", commutative: true}, // arg0 ^ arg1 compare to 0
    		{name: "TEQconst", argLength: 1, reg: gp1flags, asm: "TEQ", aux: "Int32", typ: "Flags"}, // arg0 ^ auxInt compare to 0
    		{name: "CMPF", argLength: 2, reg: fp2flags, asm: "CMPF", typ: "Flags"},                  // arg0 compare to arg1, float32
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 41K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/opGen.go

    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
    				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
    			},
    		},
    	},
    	{
    		name:    "TEQconst",
    		auxType: auxInt32,
    		argLen:  1,
    		asm:     arm.ATEQ,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
    			},
    		},
    	},
    	{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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