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Results 1 - 10 of 12 for NEGF (0.03 sec)
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src/cmd/internal/obj/mips/anames.go
"MOVDW", "MOVF", "MOVFD", "MOVFW", "MOVH", "MOVHU", "MOVW", "MOVWD", "MOVWF", "MOVWL", "MOVWR", "MSUB", "MUL", "MULD", "MULF", "MULU", "MULW", "NEGD", "NEGF", "NEGW", "NEGV", "NOOP", "NOR", "OR", "REM", "REMU", "RFE", "ROTR", "ROTRV", "SC", "SCV", "SEB", "SEH", "SGT", "SGTU", "SLL", "SQRTD", "SQRTF",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int32"}, // ^(arg0 | auxInt) {name: "NEG", argLength: 1, reg: gp11}, // -arg0 {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MASKNEZ R4, R5, R6 // a6901300 MOVFD F4, F5 // 85241901 MOVDF F4, F5 // 85181901 MOVWF F4, F5 // 85101d01 MOVFW F4, F5 // 85041b01 MOVWD F4, F5 // 85201d01 MOVDW F4, F5 // 85081b01 NEGF F4, F5 // 85141401 NEGD F4, F5 // 85181401 ABSD F4, F5 // 85081401 TRUNCDW F4, F5 // 85881a01 TRUNCFW F4, F5 // 85841a01 SQRTF F4, F5 // 85441401 SQRTD F4, F5 // 85481401
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"}, // ^(arg0 | auxInt) {name: "NEGV", argLength: 1, reg: gp11}, // -arg0 {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
{name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"}, // ^(arg0 | auxInt) {name: "NEGV", argLength: 1, reg: gp11}, // -arg0 {name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"}, // -arg0, float32 {name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "ABSD", argLength: 1, reg: fp11, asm: "ABSD"}, // abs(arg0), float64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
{VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"}, {VDIV_EQ_F32, []int{2, 1, 0}, "VDIV", "DIVF"}, {VDIV_EQ_F64, []int{2, 1, 0}, "VDIV", "DIVD"}, {VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"}, {VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"}, {VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"}, {VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"}, {VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(RSB (MUL x y) a) && buildcfg.GOARM.Version == 7 => (MULS x y a) (NEGF (MULF x y)) && buildcfg.GOARM.Version >= 6 => (NMULF x y) (NEGD (MULD x y)) && buildcfg.GOARM.Version >= 6 => (NMULD x y) (MULF (NEGF x) y) && buildcfg.GOARM.Version >= 6 => (NMULF x y) (MULD (NEGD x) y) && buildcfg.GOARM.Version >= 6 => (NMULD x y) (NMULF (NEGF x) y) => (MULF x y) (NMULD (NEGD x) y) => (MULD x y)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/internal/obj/arm/asm5.go
c.ctxt.Diag("illegal combination: %v", p) default: r = rt } } o1 |= (uint32(rf)&15)<<0 | (uint32(r)&15)<<16 | (uint32(rt)&15)<<12 case 55: /* negf freg, freg */ o1 = c.oprrr(p, p.As, int(p.Scond)) rf := int(p.From.Reg) rt := int(p.To.Reg) o1 |= (uint32(rf)&15)<<0 | (uint32(rt)&15)<<12 case 56: /* move to FP[CS]R */
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 79.4K bytes - Viewed (0)