SBC.S	$0, R5
	MOVW.P	R5, 4(R1)
E4:
	TEQ	R1, R4
	BNE	L4

	MOVW	$0, R0
	MOVW.CC	$1, R0
	MOVW	R0, c+28(FP)
	RET


// func shlVU(z, x []Word, s uint) (c Word)
TEXT ·shlVU(SB),NOSPLIT,$0
	MOVW	z_len+4(FP), R5
	TEQ	$0, R5
	BEQ	X7

	MOVW	z+0(FP), R1
	MOVW	x+12(FP), R2
	ADD	R5<<2, R2, R2
	ADD	R5<<2, R1, R5
	MOVW	s+24(FP), R3
	TEQ	$0, R3	// shift 0 is special
	BEQ	Y7

		x0 = a
	} else {
		x0 = b + 1
	}
	// arm64:"CSINC\tNE", -"CSEL"
	r0 = x0

	if cond {
		x1 = b + 1
	} else {
		x1 = a
	}
	// arm64:"CSINC\tEQ", -"CSEL"
	r1 = x1

	if cond {
		c++
	}
	// arm64:"CSINC\tEQ", -"CSEL"
	r2 = c
}

func cmovinv(cond bool, a, b int) {
	var x0, x1 int

	if cond {
		x0 = a
	} else {
		x0 = ^b
	}

	"REMU",
	"RFE",
	"SC",
	"SCV",
	"SGT",
	"SGTU",
	"SLL",
	"SQRTD",
	"SQRTF",
	"SRA",
	"SRL",
	"ROTR",
	"SUB",
	"SUBD",
	"SUBF",
	"SUBU",
	"SUBW",
	"DBAR",
	"SYSCALL",
	"TEQ",
	"TNE",
	"WORD",
	"XOR",
	"MASKEQZ",
	"MASKNEZ",
	"MOVV",
	"MOVVL",
	"MOVVR",
	"SLLV",
	"SRAV",
	"SRLV",
	"ROTRV",
	"DIVV",
	"DIVVU",
	"REMV",
	"REMVU",

// TEQ
	TEQ	$255, R7             // ff0037e3
	TEQ	$4278190080, R9      // ff0439e3
	TEQ	R9<<30, R7           // 090f37e1
	TEQ	R9>>30, R7           // 290f37e1
	TEQ	R9->30, R7           // 490f37e1
	TEQ	R9@>30, R7           // 690f37e1
	TEQ	R9<<R8, R7           // 190837e1
	TEQ	R9>>R8, R7           // 390837e1
	TEQ	R9->R8, R7           // 590837e1
	TEQ	R9@>R8, R7           // 790837e1

(TST x (SRL y z)) => (TSTshiftRLreg x y z)
(TST x (SRA y z)) => (TSTshiftRAreg x y z)
(TEQ x (SLLconst [c] y)) => (TEQshiftLL x y [c])
(TEQ x (SRLconst [c] y)) => (TEQshiftRL x y [c])
(TEQ x (SRAconst [c] y)) => (TEQshiftRA x y [c])
(TEQ x (SLL y z)) => (TEQshiftLLreg x y z)
(TEQ x (SRL y z)) => (TEQshiftRLreg x y z)
(TEQ x (SRA y z)) => (TEQshiftRAreg x y z)
(CMN x (SLLconst [c] y)) => (CMNshiftLL x y [c])

	// arm:`TST`,-`AND`
	// arm64:`TSTW`,-`AND`
	// 386:`TESTL`,-`ANDL`
	// amd64:`TESTL`,-`ANDL`
	c0 := a&b < 0
	// arm:`CMN`,-`ADD`
	// arm64:`CMNW`,-`ADD`
	c1 := a+b < 0
	// arm:`TEQ`,-`XOR`
	c2 := a^b < 0
	// arm64:`TST`,-`AND`
	// amd64:`TESTQ`,-`ANDQ`
	c3 := e&f < 0
	// arm64:`CMN`,-`ADD`
	c4 := e+f < 0
	// not optimized to single CMNW/CMN due to further use of b+d

		// remove the NOTUSETMP flag in optab.
		o1 = OP_SRR(c.opirr(-ASLLV), 0, p.From.Reg, p.To.Reg)
		o2 = OP_SRR(c.opirr(-ASRLV), 0, p.To.Reg, p.To.Reg)

	case 15: /* teq $c r,r */
		r := p.Reg
		if r == obj.REG_NONE {
			r = REGZERO
		}
		v := c.regoff(&p.From)
		/* only use 10 bits of trap code */
		o1 = OP_IRR(c.opirr(p.As), (uint32(v)&0x3FF)<<6, r, p.To.Reg)

		o2 = OP_16IRR(c.opirr(-ASRLV), uint32(32)&0x3f, uint32(p.To.Reg), uint32(p.To.Reg))

	case 15: // teq $c r,r
		v := c.regoff(&p.From)
		r := int(p.Reg)
		if r == 0 {
			r = REGZERO
		}
		/*
			teq c, r1, r2
			fallthrough
			==>
			bne r1, r2, 2
			break c
			fallthrough
		*/
		if p.As == ATEQ {

		break
	}
	// match: (TEQ x (SRL y z))
	// result: (TEQshiftRLreg x y z)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != OpARMSRL {
				continue
			}
			z := v_1.Args[1]
			y := v_1.Args[0]
			v.reset(OpARMTEQshiftRLreg)
			v.AddArg3(x, y, z)
			return true
		}
		break
	}
	// match: (TEQ x (SRA y z))

		argLen:  1,
		asm:     arm.ATST,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
			},
		},
	},
	{
		name:        "TEQ",
		argLen:      2,
		commutative: true,
		asm:         arm.ATEQ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14