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Results 1 - 9 of 9 for NEGF (0.11 sec)

  1. src/cmd/internal/obj/mips/anames.go

    	"MOVDW",
    	"MOVF",
    	"MOVFD",
    	"MOVFW",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    	"MOVWD",
    	"MOVWF",
    	"MOVWL",
    	"MOVWR",
    	"MSUB",
    	"MUL",
    	"MULD",
    	"MULF",
    	"MULU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"ROTR",
    	"ROTRV",
    	"SC",
    	"SCV",
    	"SEB",
    	"SEH",
    	"SGT",
    	"SGTU",
    	"SLL",
    	"SQRTD",
    	"SQRTF",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/loong64/anames.go

    	"MOVF",
    	"MOVFD",
    	"MOVFW",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    	"MOVWD",
    	"MOVWF",
    	"MOVWL",
    	"MOVWR",
    	"MUL",
    	"MULD",
    	"MULF",
    	"MULU",
    	"MULH",
    	"MULHU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"SC",
    	"SCV",
    	"SGT",
    	"SGTU",
    	"SLL",
    	"SQRTD",
    	"SQRTF",
    	"SRA",
    	"SRL",
    	"ROTR",
    	"SUB",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	MASKNEZ	R4, R5, R6		// a6901300
    
    	MOVFD	F4, F5			// 85241901
    	MOVDF	F4, F5			// 85181901
    	MOVWF	F4, F5			// 85101d01
    	MOVFW	F4, F5			// 85041b01
    	MOVWD	F4, F5			// 85201d01
    	MOVDW	F4, F5			// 85081b01
    	NEGF	F4, F5			// 85141401
    	NEGD	F4, F5			// 85181401
    	ABSD	F4, F5			// 85081401
    	TRUNCDW	F4, F5			// 85881a01
    	TRUNCFW	F4, F5			// 85841a01
    	SQRTF	F4, F5			// 85441401
    	SQRTD	F4, F5			// 85481401
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "NORconst", argLength: 1, reg: gp11, asm: "NOR", aux: "Int64"},                // ^(arg0 | auxInt)
    
    		{name: "NEGV", argLength: 1, reg: gp11},                // -arg0
    		{name: "NEGF", argLength: 1, reg: fp11, asm: "NEGF"},   // -arg0, float32
    		{name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"},   // -arg0, float64
    		{name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  5. src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go

    	{VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"},
    	{VDIV_EQ_F32, []int{2, 1, 0}, "VDIV", "DIVF"},
    	{VDIV_EQ_F64, []int{2, 1, 0}, "VDIV", "DIVD"},
    	{VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"},
    	{VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"},
    	{VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"},
    	{VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"},
    	{VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 11.9K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (RSB (MUL x y) a) && buildcfg.GOARM.Version == 7 => (MULS x y a)
    
    (NEGF (MULF x y)) && buildcfg.GOARM.Version >= 6 => (NMULF x y)
    (NEGD (MULD x y)) && buildcfg.GOARM.Version >= 6 => (NMULD x y)
    (MULF (NEGF x) y) && buildcfg.GOARM.Version >= 6 => (NMULF x y)
    (MULD (NEGD x) y) && buildcfg.GOARM.Version >= 6 => (NMULD x y)
    (NMULF (NEGF x) y) => (MULF x y)
    (NMULD (NEGD x) y) => (MULD x y)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/arm/asm5.go

    				c.ctxt.Diag("illegal combination: %v", p)
    			default:
    				r = rt
    			}
    		}
    
    		o1 |= (uint32(rf)&15)<<0 | (uint32(r)&15)<<16 | (uint32(rt)&15)<<12
    
    	case 55: /* negf freg, freg */
    		o1 = c.oprrr(p, p.As, int(p.Scond))
    
    		rf := int(p.From.Reg)
    		rt := int(p.To.Reg)
    
    		o1 |= (uint32(rf)&15)<<0 | (uint32(rt)&15)<<12
    
    	case 56: /* move to FP[CS]R */
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 79.4K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/rewriteARM.go

    			v.AddArg2(x, y)
    			return true
    		}
    		break
    	}
    	return false
    }
    func rewriteValueARM_OpARMMULF(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (MULF (NEGF x) y)
    	// cond: buildcfg.GOARM.Version >= 6
    	// result: (NMULF x y)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			if v_0.Op != OpARMNEGF {
    				continue
    			}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 486.8K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/opGen.go

    				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
    			},
    			outputs: []outputInfo{
    				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
    			},
    		},
    	},
    	{
    		name:   "NEGF",
    		argLen: 1,
    		asm:    arm.ANEGF,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
    			},
    			outputs: []outputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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