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Results 1 - 10 of 86 for divu (0.11 sec)
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src/cmd/cgo/internal/testcshared/testdata/main0.c
} int32_t from_pkg = FromPkg(); if (from_pkg != 1024) { fprintf(stderr, "ERROR: FromPkg=%d, want %d\n", from_pkg, 1024); return 1; } uint32_t divu = Divu(2264, 31); if (divu != 73) { fprintf(stderr, "ERROR: Divu(2264, 31)=%d, want %d\n", divu, 73); return 1; } // test.bash looks for "PASS" to ensure this program has reached the end. printf("PASS\n"); return 0;
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 12 11:59:56 UTC 2023 - 1.1K bytes - Viewed (0) -
src/cmd/cgo/internal/testcshared/testdata/p/p.go
// Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. package p import "C" //export FromPkg func FromPkg() int32 { return 1024 } //export Divu
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 12 11:59:56 UTC 2023 - 299 bytes - Viewed (0) -
test/fixedbugs/issue19507.dir/div_arm.s
// Copyright 2017 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. TEXT ·f(SB),0,$0-8 MOVW x+0(FP), R1 MOVW x+4(FP), R2 DIVU R1, R2 DIV R1, R2 MODU R1, R2 MOD R1, R2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 13 23:44:52 UTC 2018 - 271 bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
"BLTZAL", "BNE", "BREAK", "CLO", "CLZ", "CMOVF", "CMOVN", "CMOVT", "CMOVZ", "CMPEQD", "CMPEQF", "CMPGED", "CMPGEF", "CMPGTD", "CMPGTF", "DIV", "DIVD", "DIVF", "DIVU", "DIVW", "GOK", "LL", "LLV", "LUI", "MADD", "MOVB", "MOVBU", "MOVD", "MOVDF", "MOVDW", "MOVF", "MOVFD", "MOVFW", "MOVH", "MOVHU", "MOVW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
"CMPEQF", "CMPGED", "CMPGEF", "CMPGTD", "CMPGTF", "LU12IW", "LU32ID", "LU52ID", "PCALAU12I", "PCADDU12I", "JIRL", "BGE", "BLT", "BLTU", "BGEU", "DIV", "DIVD", "DIVF", "DIVU", "DIVW", "LL", "LLV", "LUI", "MOVB", "MOVBU", "MOVD", "MOVDF", "MOVDW", "MOVF", "MOVFD", "MOVFW", "MOVH", "MOVHU", "MOVW", "MOVWD", "MOVWF",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
"NMULSD", "FMULAF", "FMULAD", "FNMULAF", "FNMULAD", "FMULSF", "FMULSD", "FNMULSF", "FNMULSD", "DIVF", "DIVD", "SQRTF", "SQRTD", "ABSF", "ABSD", "NEGF", "NEGD", "SRL", "SRA", "SLL", "MULU", "DIVU", "MUL", "MMUL", "DIV", "MOD", "MODU", "DIVHW", "DIVUHW", "MOVB", "MOVBS", "MOVBU", "MOVH", "MOVHS", "MOVHU", "MOVW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/anames.go
"ADDIW", "SLLIW", "SRLIW", "SRAIW", "ADDW", "SLLW", "SRLW", "SUBW", "SRAW", "LD", "SD", "MUL", "MULH", "MULHU", "MULHSU", "MULW", "DIV", "DIVU", "REM", "REMU", "DIVW", "DIVUW", "REMW", "REMUW", "LRD", "SCD", "LRW", "SCW", "AMOSWAPD", "AMOADDD", "AMOANDD", "AMOORD", "AMOXORD", "AMOMAXD", "AMOMAXUD", "AMOMIND",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 2.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS.rules
(Mul32uhilo ...) => (MULTU ...) (Div32 x y) => (Select1 (DIV x y)) (Div32u x y) => (Select1 (DIVU x y)) (Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y))) (Div16u x y) => (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y))) (Div8 x y) => (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y))) (Div8u x y) => (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y))) (Div(32|64)F ...) => (DIV(F|D) ...) (Mod32 x y) => (Select0 (DIV x y))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 35.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MULHU R4, R5, R6 // a6101d00 REM R4, R5 // a5902000 REM R4, R5, R6 // a6902000 REMU R4, R5 // a5902100 REMU R4, R5, R6 // a6902100 DIV R4, R5 // a5102000 DIV R4, R5, R6 // a6102000 DIVU R4, R5 // a5102100 DIVU R4, R5, R6 // a6102100 SRLV R4, R5 // a5101900 SRLV R4, R5, R6 // a6101900 SRLV $4, R4, R5 // 85104500 SRLV $4, R4 // 84104500
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "DIV", argLength: 2, reg: gp2hilo, asm: "DIV", typ: "(Int32,Int32)"}, // arg0 / arg1, signed, results hi=arg0%arg1,lo=arg0/arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0)