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Results 1 - 10 of 12 for CMPEQD (0.85 sec)

  1. src/cmd/internal/obj/mips/anames.go

    	"AND",
    	"BEQ",
    	"BFPF",
    	"BFPT",
    	"BGEZ",
    	"BGEZAL",
    	"BGTZ",
    	"BLEZ",
    	"BLTZ",
    	"BLTZAL",
    	"BNE",
    	"BREAK",
    	"CLO",
    	"CLZ",
    	"CMOVF",
    	"CMOVN",
    	"CMOVT",
    	"CMOVZ",
    	"CMPEQD",
    	"CMPEQF",
    	"CMPGED",
    	"CMPGEF",
    	"CMPGTD",
    	"CMPGTF",
    	"DIV",
    	"DIVD",
    	"DIVF",
    	"DIVU",
    	"DIVW",
    	"GOK",
    	"LL",
    	"LLV",
    	"LUI",
    	"MADD",
    	"MOVB",
    	"MOVBU",
    	"MOVD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/loong64/anames.go

    	"ABSF",
    	"ADD",
    	"ADDD",
    	"ADDF",
    	"ADDU",
    	"ADDW",
    	"AND",
    	"BEQ",
    	"BGEZ",
    	"BLEZ",
    	"BGTZ",
    	"BLTZ",
    	"BFPF",
    	"BFPT",
    	"BNE",
    	"BREAK",
    	"CLO",
    	"CLZ",
    	"CMPEQD",
    	"CMPEQF",
    	"CMPGED",
    	"CMPGEF",
    	"CMPGTD",
    	"CMPGTF",
    	"LU12IW",
    	"LU32ID",
    	"LU52ID",
    	"PCALAU12I",
    	"PCADDU12I",
    	"JIRL",
    	"BGE",
    	"BLT",
    	"BLTU",
    	"BGEU",
    	"DIV",
    	"DIVD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	MOVWR	y+8(FP), R4 		// 6440402e
    	MOVWR	1(R5), R4 		// a404402e
    
    	CMPGTF	F4, R5 			// a090110c
    	CMPGTD	F4, R5 			// a090210c
    	CMPGEF	F4, R5			// a090130c
    	CMPGED	F4, R5			// a090230c
    	CMPEQD	F4, R5			// a010220c
    
    	RDTIMELW R4, R0			// 80600000
    	RDTIMEHW R4, R0			// 80640000
    	RDTIMED  R4, R5			// 85680000
    
    	MOVV    FCC0, R4		// 04dc1401
    	MOVV    R4, FCC0		// 80d81401
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 8.2K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/mips.s

    	//	LFADD freg ',' freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, int($4.Reg), &$6);
    	//	}
    	ADDD	F1, F2, F3
    
    	//	LFCMP freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	CMPEQD	F1, F2
    
    
    	//
    	// WORD
    	//
    	WORD	$1
    
    	//
    	// NOP
    	//
    	//	LNOP comma // asm doesn't support the trailing comma.
    	//	{
    	//		outcode(int($1), &nullgen, 0, &nullgen);
    	//	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    		{name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
    		{name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
    		{name: "CMPGEF", argLength: 2, reg: fp2flags, asm: "CMPGEF", typ: "Flags"}, // flags=true if arg0 >= arg1, float32
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
    		{name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
    		{name: "CMPGEF", argLength: 2, reg: fp2flags, asm: "CMPGEF", typ: "Flags"}, // flags=true if arg0 >= arg1, float32
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		{name: "CMPEQF", argLength: 2, reg: fp2flags, asm: "CMPEQF", typ: "Flags"}, // flags=true if arg0 = arg1, float32
    		{name: "CMPEQD", argLength: 2, reg: fp2flags, asm: "CMPEQD", typ: "Flags"}, // flags=true if arg0 = arg1, float64
    		{name: "CMPGEF", argLength: 2, reg: fp2flags, asm: "CMPGEF", typ: "Flags"}, // flags=true if arg0 >= arg1, float32
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LFADD freg ',' freg ',' freg
    //	{
    //		outcode(int($1), &$2, int($4.Reg), &$6);
    //	}
    	ADDD	F1, F2, F3
    
    //	LFCMP freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	CMPEQD	F1, F2
    
    
    //
    // WORD
    //
    	WORD	$1	// 00000001
    	NOOP		// 00000000
    	SYNC		// 0000000f
    
    //
    // NOP
    //
    //	LNOP comma // asm doesn't support the trailing comma.
    //	{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteMIPS.go

    		v.AddArg(v0)
    		return true
    	}
    }
    func rewriteValueMIPS_OpEq64F(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Eq64F x y)
    	// result: (FPFlagTrue (CMPEQD x y))
    	for {
    		x := v_0
    		y := v_1
    		v.reset(OpMIPSFPFlagTrue)
    		v0 := b.NewValue0(v.Pos, OpMIPSCMPEQD, types.TypeFlags)
    		v0.AddArg2(x, y)
    		v.AddArg(v0)
    		return true
    	}
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 176.6K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    		v.AddArg2(v0, v1)
    		return true
    	}
    }
    func rewriteValueLOONG64_OpEq64F(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Eq64F x y)
    	// result: (FPFlagTrue (CMPEQD x y))
    	for {
    		x := v_0
    		y := v_1
    		v.reset(OpLOONG64FPFlagTrue)
    		v0 := b.NewValue0(v.Pos, OpLOONG64CMPEQD, types.TypeFlags)
    		v0.AddArg2(x, y)
    		v.AddArg(v0)
    		return true
    	}
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
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