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Results 1 - 10 of 159 for divd (0.03 sec)
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test/codegen/arithmetic.go
d += e } return d, e } func NoFix32A(divr int32) (int32, int32) { var d int32 = 42 var e int32 = 84 if divr > 5 { // amd64:-"JMP" // 386:-"JMP" d /= divr // amd64:-"JMP" // 386:-"JMP" e %= divr d += e } return d, e } func NoFix32B(divd int32) (int32, int32) { var d int32 var e int32 var divr int32 = -1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
test/codegen/floats.go
// 386/sse2:"MULSD",-"DIVSD" // amd64:"MULSD",-"DIVSD" // arm/7:"MULD",-"DIVD" // arm64:"FMULD",-"FDIVD" // ppc64x:"FMUL",-"FDIV" // riscv64:"FMULD",-"FDIVD" x := f1 / 16.0 // 386/sse2:"MULSD",-"DIVSD" // amd64:"MULSD",-"DIVSD" // arm/7:"MULD",-"DIVD" // arm64:"FMULD",-"FDIVD" // ppc64x:"FMUL",-"FDIVD" // riscv64:"FMULD",-"FDIVD" y := f2 / 0.125
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 15:24:29 UTC 2024 - 4.9K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
"BLTZAL", "BNE", "BREAK", "CLO", "CLZ", "CMOVF", "CMOVN", "CMOVT", "CMOVZ", "CMPEQD", "CMPEQF", "CMPGED", "CMPGEF", "CMPGTD", "CMPGTF", "DIV", "DIVD", "DIVF", "DIVU", "DIVW", "GOK", "LL", "LLV", "LUI", "MADD", "MOVB", "MOVBU", "MOVD", "MOVDF", "MOVDW", "MOVF", "MOVFD", "MOVFW", "MOVH", "MOVHU", "MOVW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armv6.s
FNMULAF F5, F6, F7 // 457a96ee FNMULAD F5, F6, F7 // 457b96ee FNMULSF F5, F6, F7 // 057a96ee FNMULSD F5, F6, F7 // 057b96ee DIVF F0, F1, F2 // 002a81ee DIVD.EQ F3, F4, F5 // 035b840e DIVF.NE F0, F2 // 002a821e DIVD F3, F5 // 035b85ee NEGF F0, F1 // 401ab1ee NEGD F4, F5 // 445bb1ee ABSF F0, F1 // c01ab0ee ABSD F4, F5 // c45bb0ee
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Dec 21 16:30:51 UTC 2017 - 4.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
"NMULSD", "FMULAF", "FMULAD", "FNMULAF", "FNMULAD", "FMULSF", "FMULSD", "FNMULSF", "FNMULSD", "DIVF", "DIVD", "SQRTF", "SQRTD", "ABSF", "ABSD", "NEGF", "NEGD", "SRL", "SRA", "SLL", "MULU", "DIVU", "MUL", "MMUL", "DIV", "MOD", "MODU", "DIVHW", "DIVUHW", "MOVB", "MOVBS", "MOVBU", "MOVH", "MOVHS", "MOVHU", "MOVW",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
"CMPEQF", "CMPGED", "CMPGEF", "CMPGTD", "CMPGTF", "LU12IW", "LU32ID", "LU52ID", "PCALAU12I", "PCADDU12I", "JIRL", "BGE", "BLT", "BLTU", "BGEU", "DIV", "DIVD", "DIVF", "DIVU", "DIVW", "LL", "LLV", "LUI", "MOVB", "MOVBU", "MOVD", "MOVDF", "MOVDW", "MOVF", "MOVFD", "MOVFW", "MOVH", "MOVHU", "MOVW", "MOVWD", "MOVWF",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"FSQRT", "FSQRTCC", "FSQRTS", "FSQRTSCC", "CNTLZD", "CNTLZDCC", "CMPW", "CMPWU", "CMPB", "FTDIV", "FTSQRT", "DIVD", "DIVDCC", "DIVDE", "DIVDECC", "DIVDEU", "DIVDEUCC", "DIVDVCC", "DIVDV", "DIVDU", "DIVDUCC", "DIVDUVCC", "DIVDUV", "EXTSW", "EXTSWCC", "FCFID", "FCFIDCC", "FCFIDU", "FCFIDUCC", "FCFIDS",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
return true case MULLW, MULLWCC, MULHW, MULHWCC, MULLD, MULLDCC, MULHD, MULHDCC, MULLWO, MULLWOCC, MULHWU, MULHWUCC, MULLDO, MULLDOCC: return true case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC: return true case MODUD, MODSD, MODUW, MODSW: return true
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
MLGR R1, R2 // b9860021 DIVD R1, R2 // b90400b2b90d00a1b904002b DIVD R1, R2, R3 // b90400b2b90d00a1b904003b DIVW R4, R5 // b90400b5b91d00a4b904005b DIVW R4, R5, R6 // b90400b5b91d00a4b904006b DIVDU R7, R8 // a7a90000b90400b8b98700a7b904008b DIVDU R7, R8, R9 // a7a90000b90400b8b98700a7b904009b
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0)