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Results 1 - 10 of 11 for MULD (0.24 sec)

  1. test/codegen/floats.go

    	// 386/sse2:"ADDSD",-"MULSD"
    	// amd64:"ADDSD",-"MULSD"
    	// arm/7:"ADDD",-"MULD"
    	// arm64:"FADDD",-"FMULD"
    	// ppc64x:"FADD",-"FMUL"
    	// riscv64:"FADDD",-"FMULD"
    	return f * 2.0
    }
    
    func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIV"
    	// riscv64:"FMULD",-"FDIVD"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/mips/anames.go

    	"MADD",
    	"MOVB",
    	"MOVBU",
    	"MOVD",
    	"MOVDF",
    	"MOVDW",
    	"MOVF",
    	"MOVFD",
    	"MOVFW",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    	"MOVWD",
    	"MOVWF",
    	"MOVWL",
    	"MOVWR",
    	"MSUB",
    	"MUL",
    	"MULD",
    	"MULF",
    	"MULU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"ROTR",
    	"ROTRV",
    	"SC",
    	"SCV",
    	"SEB",
    	"SEH",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/loong64/anames.go

    	"LLV",
    	"LUI",
    	"MOVB",
    	"MOVBU",
    	"MOVD",
    	"MOVDF",
    	"MOVDW",
    	"MOVF",
    	"MOVFD",
    	"MOVFW",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    	"MOVWD",
    	"MOVWF",
    	"MOVWL",
    	"MOVWR",
    	"MUL",
    	"MULD",
    	"MULF",
    	"MULU",
    	"MULH",
    	"MULHU",
    	"MULW",
    	"NEGD",
    	"NEGF",
    	"NEGW",
    	"NEGV",
    	"NOOP",
    	"NOR",
    	"OR",
    	"REM",
    	"REMU",
    	"RFE",
    	"SC",
    	"SCV",
    	"SGT",
    	"SGTU",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 02:04:54 UTC 2024
    - 1.9K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    		{name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"},                    // arg0 - arg1
    		{name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		{name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"},                    // arg0 - arg1
    		{name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		{name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"},                    // arg0 - arg1
    		{name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true}, // arg0 * arg1
    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1
    		{name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"},                    // arg0 / arg1
    		{name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"},                    // arg0 / arg1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  7. src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go

    	{VSUB_EQ_F32, []int{2, 1, 0}, "VSUB", "SUBF"},
    	{VSUB_EQ_F64, []int{2, 1, 0}, "VSUB", "SUBD"},
    	{VMUL_EQ_F32, []int{2, 1, 0}, "VMUL", "MULF"},
    	{VMUL_EQ_F64, []int{2, 1, 0}, "VMUL", "MULD"},
    	{VNMUL_EQ_F32, []int{2, 1, 0}, "VNMUL", "NMULF"},
    	{VNMUL_EQ_F64, []int{2, 1, 0}, "VNMUL", "NMULD"},
    	{VMLA_EQ_F32, []int{2, 1, 0}, "VMLA", "MULAF"},
    	{VMLA_EQ_F64, []int{2, 1, 0}, "VMLA", "MULAD"},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Oct 19 23:33:33 UTC 2023
    - 11.9K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/ARMOps.go

    		{name: "SUBD", argLength: 2, reg: fp21, asm: "SUBD"},                      // arg0 - arg1
    		{name: "MULF", argLength: 2, reg: fp21, asm: "MULF", commutative: true},   // arg0 * arg1
    		{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true},   // arg0 * arg1
    		{name: "NMULF", argLength: 2, reg: fp21, asm: "NMULF", commutative: true}, // -(arg0 * arg1)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Feb 24 00:21:13 UTC 2023
    - 41K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/_gen/ARM.rules

    (NEGF (MULF x y)) && buildcfg.GOARM.Version >= 6 => (NMULF x y)
    (NEGD (MULD x y)) && buildcfg.GOARM.Version >= 6 => (NMULD x y)
    (MULF (NEGF x) y) && buildcfg.GOARM.Version >= 6 => (NMULF x y)
    (MULD (NEGD x) y) && buildcfg.GOARM.Version >= 6 => (NMULD x y)
    (NMULF (NEGF x) y) => (MULF x y)
    (NMULD (NEGD x) y) => (MULD x y)
    
    // the result will overwrite the addend, since they are in the same register
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 90.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewriteARM.go

    			v.AddArg3(x, y, a)
    			return true
    		}
    		break
    	}
    	return false
    }
    func rewriteValueARM_OpARMADDD(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (ADDD a (MULD x y))
    	// cond: a.Uses == 1 && buildcfg.GOARM.Version >= 6
    	// result: (MULAD a x y)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			a := v_0
    			if v_1.Op != OpARMMULD {
    				continue
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Nov 20 17:19:36 UTC 2023
    - 486.8K bytes
    - Viewed (0)
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