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Results 1 - 10 of 40 for divlu (0.06 sec)
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src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
"SUBW", "DBAR", "SYSCALL", "TEQ", "TNE", "WORD", "XOR", "MASKEQZ", "MASKNEZ", "MOVV", "MOVVL", "MOVVR", "SLLV", "SRAV", "SRLV", "ROTRV", "DIVV", "DIVVU", "REMV", "REMVU", "MULV", "MULVU", "MULHV", "MULHVU", "ADDV", "ADDVU", "SUBV", "SUBVU", "TRUNCFV", "TRUNCDV", "TRUNCFW", "TRUNCDW", "MOVWU", "MOVFV",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
{name: "DIVL", argLength: 2, reg: gp11div, typ: "(Int32,Int32)", asm: "IDIVL", aux: "Bool", clobberFlags: true}, {name: "DIVW", argLength: 2, reg: gp11div, typ: "(Int16,Int16)", asm: "IDIVW", aux: "Bool", clobberFlags: true}, {name: "DIVQU", argLength: 2, reg: gp11div, typ: "(UInt64,UInt64)", asm: "DIVQ", clobberFlags: true},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
REMV R4, R5 // a5902200 REMV R4, R5, R6 // a6902200 REMVU R4, R5 // a5902300 REMVU R4, R5, R6 // a6902300 DIVV R4, R5 // a5102200 DIVV R4, R5, R6 // a6102200 DIVVU R4, R5 // a5102300 DIVVU R4, R5, R6 // a6102300 MOVH R4, result+16(FP) // 64604029 MOVH R4, 1(R5) // a4044029 MOVH y+8(FP), R4 // 64404028 MOVH 1(R5), R4 // a4044028 MOVHU R4, R5 // 8500cf00
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/anames.go
"CMP", "CMPU", "CMPEQB", "CNTLZW", "CNTLZWCC", "CRAND", "CRANDN", "CREQV", "CRNAND", "CRNOR", "CROR", "CRORN", "CRXOR", "DIVW", "DIVWCC", "DIVWVCC", "DIVWV", "DIVWU", "DIVWUCC", "DIVWUVCC", "DIVWUV", "MODUD", "MODUW", "MODSD", "MODSW", "EQV", "EQVCC", "EXTSB", "EXTSBCC", "EXTSH", "EXTSHCC", "FABS", "FABSCC", "FADD",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 7.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
DIVW R4, R5 // b90400b5b91d00a4b904005b DIVW R4, R5, R6 // b90400b5b91d00a4b904006b DIVDU R7, R8 // a7a90000b90400b8b98700a7b904008b DIVDU R7, R8, R9 // a7a90000b90400b8b98700a7b904009b DIVWU R1, R2 // a7a90000b90400b2b99700a1b904002b DIVWU R1, R2, R3 // a7a90000b90400b2b99700a1b904003b MODD R1, R2 // b90400b2b90d00a1b904002a
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
(Div64u x y) => (Select1 (DIVVU x y)) (Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y))) (Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))) (Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y))) (Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))) (Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
(Div64 x y) => (DIVV x y) (Div64u ...) => (DIVVU ...) (Div32 x y) => (DIVV (SignExt32to64 x) (SignExt32to64 y)) (Div32u x y) => (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)) (Div16 x y) => (DIVV (SignExt16to64 x) (SignExt16to64 y)) (Div16u x y) => (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)) (Div8 x y) => (DIVV (SignExt8to64 x) (SignExt8to64 y)) (Div8u x y) => (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y)) (Div(32|64)F ...) => (DIV(F|D) ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
test/codegen/arithmetic.go
func Pow2DivisibleSigned(n1, n2 int) (bool, bool) { // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA" // arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND" // ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP" a := n1%64 == 0 // signed divisible // 386:"TESTL\t[$]63",-"DIVL",-"SHRL" // amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ" // arm:"AND\t[$]63",-".*udiv",-"SRA"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0)