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Results 1 - 10 of 10 for SQRTF (0.11 sec)
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test/codegen/math.go
return math.Sqrt(x) } func sqrt32(x float32) float32 { // amd64:"SQRTSS" // 386/sse2:"SQRTSS" 386/softfloat:-"SQRTS" // arm64:"FSQRTS" // arm/7:"SQRTF" // mips/hardfloat:"SQRTF" mips/softfloat:-"SQRTF" // mips64/hardfloat:"SQRTF" mips64/softfloat:-"SQRTF" // wasm:"F32Sqrt" // ppc64x:"FSQRTS" // riscv64: "FSQRTS" return float32(math.Sqrt(float64(x))) } // Check that it's using integer registers
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Apr 04 15:24:29 UTC 2024 - 6.2K bytes - Viewed (0) -
src/cmd/internal/obj/mips/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 1.4K bytes - Viewed (0) -
src/cmd/internal/obj/loong64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 1.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
MOVWD F4, F5 // 85201d01 MOVDW F4, F5 // 85081b01 NEGF F4, F5 // 85141401 NEGD F4, F5 // 85181401 ABSD F4, F5 // 85081401 TRUNCDW F4, F5 // 85881a01 TRUNCFW F4, F5 // 85841a01 SQRTF F4, F5 // 85441401 SQRTD F4, F5 // 85481401 DBAR // 00007238 NOOP // 00004003 MOVWR R4, result+16(FP) // 6460402f MOVWR R4, 1(R5) // a404402f MOVWR y+8(FP), R4 // 6440402e
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 8.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "NEGD", argLength: 1, reg: fp11, asm: "NEGD"}, // -arg0, float64 {name: "SQRTD", argLength: 1, reg: fp11, asm: "SQRTD"}, // sqrt(arg0), float64 {name: "SQRTF", argLength: 1, reg: fp11, asm: "SQRTF"}, // sqrt(arg0), float32 {name: "MASKEQZ", argLength: 2, reg: gp21, asm: "MASKEQZ"}, // returns 0 if arg1 == 0, otherwise returns arg0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
{VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"}, {VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"}, {VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"}, {VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"}, {VSQRT_EQ_F32, []int{1, 0}, "VSQRT", "SQRTF"}, {VSQRT_EQ_F64, []int{1, 0}, "VSQRT", "SQRTD"}, {VCMP_EQ_F32, []int{1, 0}, "VCMP", "CMPF"}, {VCMP_EQ_F64, []int{1, 0}, "VCMP", "CMPD"}, {VCMP_E_EQ_F32, []int{1, 0}, "VCMP.E", "CMPF"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64.rules
// unary ops (Neg(64|32|16|8) ...) => (NEGV ...) (Neg(32|64)F ...) => (NEG(F|D) ...) (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) // boolean ops -- booleans are represented with 0=false, 1=true (AndB ...) => (AND ...) (OrB ...) => (OR ...) (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y)) (NeqB ...) => (XOR ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:26:25 UTC 2023 - 31.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64.rules
// unary ops (Neg(64|32|16|8) ...) => (NEGV ...) (Neg(32|64)F ...) => (NEG(F|D) ...) (Com(64|32|16|8) x) => (NOR (MOVVconst [0]) x) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) // boolean ops -- booleans are represented with 0=false, 1=true (AndB ...) => (AND ...) (OrB ...) => (OR ...) (EqB x y) => (XOR (MOVVconst [1]) (XOR <typ.Bool> x y)) (NeqB ...) => (XOR ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 31 03:59:48 UTC 2023 - 41.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM.rules
(Xor(32|16|8) ...) => (XOR ...) // unary ops (Neg(32|16|8) x) => (RSBconst [0] x) (Neg(32|64)F ...) => (NEG(F|D) ...) (Com(32|16|8) ...) => (MVN ...) (Sqrt ...) => (SQRTD ...) (Sqrt32 ...) => (SQRTF ...) (Abs ...) => (ABSD ...) // TODO: optimize this for ARMv5 and ARMv6 (Ctz32NonZero ...) => (Ctz32 ...) (Ctz16NonZero ...) => (Ctz32 ...) (Ctz8NonZero ...) => (Ctz32 ...)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, }, }, { name: "SQRTF", argLen: 1, asm: arm.ASQRTF, reg: regInfo{ inputs: []inputInfo{ {0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 }, outputs: []outputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)