SLW - Code Search

src/cmd/internal/obj/ppc64/anames.go

	"NEGV",
	"NOR",
	"NORCC",
	"OR",
	"ORCC",
	"ORN",
	"ORNCC",
	"ORIS",
	"REM",
	"REMU",
	"RFI",
	"RLWMI",
	"RLWMICC",
	"RLWNM",
	"RLWNMCC",
	"CLRLSLWI",
	"SLW",
	"SLWCC",
	"SRW",
	"SRAW",
	"SRAWCC",
	"SRWCC",
	"STBCCC",
	"STHCCC",
	"STSW",
	"STWCCC",
	"SUB",
	"SUBCC",
	"SUBVCC",
	"SUBC",
	"SUBCCC",
	"SUBCV",
	"SUBCVCC",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Mon Apr 01 18:50:29 UTC 2024

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github.com/golang/go

src/cmd/internal/obj/s390x/anames.go

	"MOVDBR",
	"MOVDEQ",
	"MOVDGE",
	"MOVDGT",
	"MOVDLE",
	"MOVDLT",
	"MOVDNE",
	"LOCR",
	"LOCGR",
	"FLOGR",
	"POPCNT",
	"AND",
	"ANDW",
	"OR",
	"ORW",
	"XOR",
	"XORW",
	"SLW",
	"SLD",
	"SRW",
	"SRAW",
	"SRD",
	"SRAD",
	"RLL",
	"RLLG",
	"RNSBG",
	"RXSBG",
	"ROSBG",
	"RNSBGT",
	"RXSBGT",
	"ROSBGT",
	"RISBG",
	"RISBGN",
	"RISBGZ",
	"RISBGNZ",

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Tue Sep 05 16:41:03 UTC 2023

- 7.1K bytes

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github.com/golang/go

src/cmd/compile/internal/ssa/rewriteS390X.go

		v.AddArg2(x, y)
		return true
	}
	// match: (SLW x (MOVWreg y))
	// result: (SLW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVWreg {
			break
		}
		y := v_1.Args[0]
		v.reset(OpS390XSLW)
		v.AddArg2(x, y)
		return true
	}
	// match: (SLW x (MOVHreg y))
	// result: (SLW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVHreg {

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Oct 12 18:09:26 UTC 2023

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/s390x.s

	SRD	$4, R4, R7              // eb740004000c
	SRD	R1, R4, R7              // eb741000000c
	SRW	$4, R4, R7              // eb74000400de
	SRW	R1, R4, R7              // eb74100000de
	SLW	$4, R3, R6              // eb63000400df
	SLW	R2, R3, R6              // eb63200000df
	SLD	$4, R3, R6              // eb630004000d
	SLD	R2, R3, R6              // eb632000000d
	SRAD	$4, R5, R8              // eb850004000a

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed Nov 22 03:55:32 UTC 2023

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/S390X.rules

// Lower bounded shifts first. No need to check shift value.
(Lsh64x(64|32|16|8)  x y) && shiftIsBounded(v) => (SLD x y)
(Lsh32x(64|32|16|8)  x y) && shiftIsBounded(v) => (SLW x y)
(Lsh16x(64|32|16|8)  x y) && shiftIsBounded(v) => (SLW x y)
(Lsh8x(64|32|16|8)   x y) && shiftIsBounded(v) => (SLW x y)
(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Oct 12 18:09:26 UTC 2023

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github.com/golang/go

src/internal/runtime/atomic/atomic_s390x.s

	// containing v to OR with the entire word atomically.
	MOVD	$(3<<3), R5
	RXSBG	$59, $60, $3, R3, R5 // R5 = 24 - ((addr % 4) * 8) = ((addr & 3) << 3) ^ (3 << 3)
	ANDW	$~3, R3              // R3 = floor(addr, 4) = addr &^ 3
	SLW	R5, R4               // R4 = uint32(v) << R5
	LAO	R4, R6, 0(R3)        // R6 = *R3; *R3 |= R4; (atomic)
	RET

// func And8(addr *uint8, v uint8)
TEXT ·And8(SB), NOSPLIT, $0-9
	MOVD	ptr+0(FP), R3

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Mon Mar 25 19:53:03 UTC 2024

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github.com/golang/go

src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

		{name: "SRW", argLength: 2, reg: gp21, asm: "SRW"},       // unsigned arg0 >> (arg1&63), 32 bit width
		{name: "SLD", argLength: 2, reg: gp21, asm: "SLD"},       // arg0 << (arg1&127), 64 bit width
		{name: "SLW", argLength: 2, reg: gp21, asm: "SLW"},       // arg0 << (arg1&63), 32 bit width

		{name: "ROTL", argLength: 2, reg: gp21, asm: "ROTL"},   // arg0 rotate left by arg1 mod 64

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Wed May 22 19:59:38 UTC 2024

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github.com/golang/go

test/codegen/shift.go

	return int64(v) >> 16
}

func rshConst64x64Overflow8(v int8) int64 {
	// riscv64:"SLLI","SRAI",-"SRAIW"
	return int64(v) >> 8
}

func lshConst32x64(v int32) int32 {
	// ppc64x:"SLW"
	// riscv64:"SLLI",-"AND",-"SLTIU", -"MOVW"
	return v << uint64(29)
}

func rshConst32Ux64(v uint32) uint32 {
	// ppc64x:"SRW"
	// riscv64:"SRLIW",-"AND",-"SLTIU", -"MOVW"
	return v >> uint64(29)
}

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Tue May 21 18:53:43 UTC 2024

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github.com/golang/go

test/codegen/memcombine.go

	// s390x:`MOVHZ\s\(.*\),`,-`OR`,-`ORW`,-`SLD`,-`SLW`
	return binary.BigEndian.Uint16(b)
}

func load_be16_idx(b []byte, idx int) uint16 {
	// amd64:`ROLW\s\$8`,-`MOVB`,-`OR`
	// arm64:`REV16W`,`MOVHU\s\(R[0-9]+\)\(R[0-9]+\),`,-`MOVB`
	// ppc64le:`MOVHBR`,-`MOVBZ`
	// ppc64:`MOVHZ`,-`MOVBZ`
	// s390x:`MOVHZ\s\(.*\)\(.*\*1\),`,-`OR`,-`ORW`,-`SLD`,-`SLW`
	return binary.BigEndian.Uint16(b[idx:])
}

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Thu Mar 21 19:45:41 UTC 2024

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github.com/golang/go

src/cmd/asm/internal/asm/testdata/ppc64.s

	MODUD R3, R4, R5                // 7ca41a12
	MODUW R3, R4, R5                // 7ca41a16
	MODSD R3, R4, R5                // 7ca41e12
	MODSW R3, R4, R5                // 7ca41e16

	SLW $8, R3, R4                  // 5464402e
	SLW R3, R4, R5                  // 7c851830
	SLWCC R3, R4                    // 7c841831
	SLD $16, R3, R4                 // 786483e4
	SLD R3, R4, R5                  // 7c851836

Registered: Wed Jun 12 16:32:35 UTC 2024

- Last Modified: Fri May 17 21:53:50 UTC 2024

- 50.2K bytes

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