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Results 1 - 10 of 33 for umul (0.03 sec)

  1. src/cmd/internal/obj/arm64/anames.go

    	"UBFIZ",
    	"UBFIZW",
    	"UBFM",
    	"UBFMW",
    	"UBFX",
    	"UBFXW",
    	"UCVTFD",
    	"UCVTFS",
    	"UCVTFWD",
    	"UCVTFWS",
    	"UDIV",
    	"UDIVW",
    	"UMADDL",
    	"UMNEGL",
    	"UMSUBL",
    	"UMULH",
    	"UMULL",
    	"UREM",
    	"UREMW",
    	"UXTB",
    	"UXTBW",
    	"UXTH",
    	"UXTHW",
    	"UXTW",
    	"VADD",
    	"VADDP",
    	"VADDV",
    	"VAND",
    	"VBCAX",
    	"VBIF",
    	"VBIT",
    	"VBSL",
    	"VCMEQ",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  2. src/net/interface_windows.go

    		index := aa.IfIndex
    		if index == 0 { // ipv6IfIndex is a substitute for ifIndex
    			index = aa.Ipv6IfIndex
    		}
    		if ifi == nil || ifi.Index == int(index) {
    			for pmul := aa.FirstMulticastAddress; pmul != nil; pmul = pmul.Next {
    				sa, err := pmul.Address.Sockaddr.Sockaddr()
    				if err != nil {
    					return nil, os.NewSyscallError("sockaddr", err)
    				}
    				switch sa := sa.(type) {
    				case *syscall.SockaddrInet4:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 15 10:25:02 UTC 2024
    - 5.5K bytes
    - Viewed (0)
  3. src/crypto/internal/bigmod/nat_arm64.s

    	LDP	(R1), (R9, R10)
    	ADDS	R4, R9
    	MUL	R6, R3, R14
    	ADCS	R14, R10
    	MUL	R7, R3, R15
    	LDP	16(R1), (R11, R12)
    	ADCS	R15, R11
    	MUL	R8, R3, R16
    	ADCS	R16, R12
    	UMULH	R8, R3, R20
    	ADC	$0, R20
    
    	MUL	R5, R3, R13
    	ADDS	R13, R9
    	UMULH	R5, R3, R17
    	ADCS	R17, R10
    	UMULH	R6, R3, R21
    	STP.P	(R9, R10), 16(R1)
    	ADCS	R21, R11
    	UMULH	R7, R3, R19
    	ADCS	R19, R12
    	STP.P	(R11, R12), 16(R1)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 22:37:58 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  4. test/codegen/floats.go

    	// arm/7:"ADDD",-"MULD"
    	// arm64:"FADDD",-"FMULD"
    	// ppc64x:"FADD",-"FMUL"
    	// riscv64:"FADDD",-"FMULD"
    	return f * 2.0
    }
    
    func DivPow2(f1, f2, f3 float64) (float64, float64, float64) {
    	// 386/sse2:"MULSD",-"DIVSD"
    	// amd64:"MULSD",-"DIVSD"
    	// arm/7:"MULD",-"DIVD"
    	// arm64:"FMULD",-"FDIVD"
    	// ppc64x:"FMUL",-"FDIV"
    	// riscv64:"FMULD",-"FDIVD"
    	x := f1 / 16.0
    
    	// 386/sse2:"MULSD",-"DIVSD"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  5. test/fixedbugs/issue28688.go

    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    package main
    
    import (
    	"fmt"
    )
    
    // When using soft-float, OMUL might be rewritten to function
    // call so we should ensure it was evaluated first. Stack frame
    // setup for "test" function call should happen after call to runtime.fmul32
    
    var x int32 = 1
    
    func main() {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 03 16:14:24 UTC 2021
    - 622 bytes
    - Viewed (0)
  6. src/math/exp_s390x.s

    	LDGR	R2, F0
    	FMADD	F0, F4, F0
    	MOVD	$·expx4ff<>+0(SB), R3
    	FMOVD	0(R3), F2
    	FMUL	F2, F0
    	FMOVD	F0, ret+8(FP)
    	RET
    L13:
    	FMOVD	$0, F0
    	FMOVD	F0, ret+8(FP)
    	RET
    L21:
    	ADDW	$0x1000, R1
    	RISBGN	$0, $15, $48, R1, R2
    	LDGR	R2, F0
    	FMADD	F0, F4, F0
    	MOVD	$·expx2ff<>+0(SB), R3
    	FMOVD	0(R3), F2
    	FMUL	F2, F0
    	FMOVD	F0, ret+8(FP)
    	RET
    LEXITTAGexp:
    	FMOVD	F0, ret+8(FP)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 4.6K bytes
    - Viewed (0)
  7. src/math/sinh_s390x.s

    	BEQ     L9
    	WFMSDB  V0, V1, V6, V0
    	MOVD    $sinhx4ff<>+0(SB), R3
    	FNEG    F0, F0
    	FMOVD   0(R3), F2
    	FMUL    F2, F0
    	ANDW    $0xFFFF, R2
    	WORD    $0xA53FEFB6     //llill %r3,61366
    	SUBW    R2, R3, R2
    	RISBGN	$0, $15, $48, R2, R1
    	LDGR    R1, F2
    	FMUL    F2, F0
    	FMOVD   F0, ret+8(FP)
    	RET
    
    L20:
    	MOVD    $sinhxadd<>+0(SB), R2
    	FMOVD   0(R2), F2
    	MOVD    sinhrlog2<>+0(SB), R2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 17 13:54:10 UTC 2021
    - 6K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/arch/mips.go

    		return true
    	}
    	return false
    }
    
    // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is
    // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
    func IsMIPSMUL(op obj.As) bool {
    	switch op {
    	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
    		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
    		mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU,
    		mips.AMADD, mips.AMSUB:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 04 19:06:44 UTC 2020
    - 1.7K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/arm/anames.go

    	"FMULSF",
    	"FMULSD",
    	"FNMULSF",
    	"FNMULSD",
    	"DIVF",
    	"DIVD",
    	"SQRTF",
    	"SQRTD",
    	"ABSF",
    	"ABSD",
    	"NEGF",
    	"NEGD",
    	"SRL",
    	"SRA",
    	"SLL",
    	"MULU",
    	"DIVU",
    	"MUL",
    	"MMUL",
    	"DIV",
    	"MOD",
    	"MODU",
    	"DIVHW",
    	"DIVUHW",
    	"MOVB",
    	"MOVBS",
    	"MOVBU",
    	"MOVH",
    	"MOVHS",
    	"MOVHU",
    	"MOVW",
    	"MOVM",
    	"SWPBU",
    	"SWPW",
    	"RFE",
    	"SWI",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  10. tensorflow/compiler/mlir/lite/stablehlo/tests/legalize-tfl-stablehlo-mul.mlir

    Eugene Burmako <******@****.***> 1671166704 -0800
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Fri Dec 16 05:09:09 UTC 2022
    - 751 bytes
    - Viewed (0)
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