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Results 1 - 10 of 224 for madd (0.04 sec)

  1. src/vendor/golang.org/x/net/idna/punycode.go

    			if !ok {
    				return "", punyError(encoded)
    			}
    			pos++
    			i, overflow = madd(i, digit, w)
    			if overflow {
    				return "", punyError(encoded)
    			}
    			t := k - bias
    			if k <= bias {
    				t = tmin
    			} else if k >= bias+tmax {
    				t = tmax
    			}
    			if digit < t {
    				break
    			}
    			w, overflow = madd(0, w, base-t)
    			if overflow {
    				return "", punyError(encoded)
    			}
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 09 20:10:36 UTC 2021
    - 4.6K bytes
    - Viewed (0)
  2. src/crypto/internal/edwards25519/field/fe_arm64.s

    	AND $0x7ffffffffffff, R1, R11
    	AND $0x7ffffffffffff, R2, R12
    	AND $0x7ffffffffffff, R3, R13
    	AND $0x7ffffffffffff, R4, R14
    
    	ADD R0>>51, R11, R11
    	ADD R1>>51, R12, R12
    	ADD R2>>51, R13, R13
    	ADD R3>>51, R14, R14
    	// R4>>51 * 19 + R10 -> R10
    	LSR $51, R4, R21
    	MOVD $19, R22
    	MADD R22, R10, R21, R10
    
    	STP (R10, R11), 0(R20)
    	STP (R12, R13), 16(R20)
    	MOVD R14, 32(R20)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 04 17:29:44 UTC 2024
    - 1K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/arch/mips.go

    // IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is
    // one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
    func IsMIPSMUL(op obj.As) bool {
    	switch op {
    	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
    		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
    		mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU,
    		mips.AMADD, mips.AMSUB:
    		return true
    	}
    	return false
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 04 19:06:44 UTC 2020
    - 1.7K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/mips/anames.go

    	"CMOVZ",
    	"CMPEQD",
    	"CMPEQF",
    	"CMPGED",
    	"CMPGEF",
    	"CMPGTD",
    	"CMPGTF",
    	"DIV",
    	"DIVD",
    	"DIVF",
    	"DIVU",
    	"DIVW",
    	"GOK",
    	"LL",
    	"LLV",
    	"LUI",
    	"MADD",
    	"MOVB",
    	"MOVBU",
    	"MOVD",
    	"MOVDF",
    	"MOVDW",
    	"MOVF",
    	"MOVFD",
    	"MOVFW",
    	"MOVH",
    	"MOVHU",
    	"MOVW",
    	"MOVWD",
    	"MOVWF",
    	"MOVWL",
    	"MOVWR",
    	"MSUB",
    	"MUL",
    	"MULD",
    	"MULF",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 1.4K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/arm64/doc.go

    	MOVD R29, 384(R19)    <=>    str x29, [x19,#384]
    	MOVB.P R30, 30(R4)    <=>    strb w30, [x4],#30
    	STLRH R21, (R19)      <=>    stlrh w21, [x19]
    
    (2) MADD, MADDW, MSUB, MSUBW, SMADDL, SMSUBL, UMADDL, UMSUBL <Rm>, <Ra>, <Rn>, <Rd>
    
    Examples:
    
    	MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
    	SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 07 00:21:42 UTC 2023
    - 9.6K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/arm64/anames.go

    	"LDORLH",
    	"LDORLW",
    	"LDORW",
    	"LDP",
    	"LDPSW",
    	"LDPW",
    	"LDXP",
    	"LDXPW",
    	"LDXR",
    	"LDXRB",
    	"LDXRH",
    	"LDXRW",
    	"LSL",
    	"LSLW",
    	"LSR",
    	"LSRW",
    	"MADD",
    	"MADDW",
    	"MNEG",
    	"MNEGW",
    	"MOVB",
    	"MOVBU",
    	"MOVD",
    	"MOVH",
    	"MOVHU",
    	"MOVK",
    	"MOVKW",
    	"MOVN",
    	"MOVNW",
    	"MOVP",
    	"MOVPD",
    	"MOVPQ",
    	"MOVPS",
    	"MOVPSW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/mips.s

    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	ADD	R1, R2, R3
    
    	//	LADDW imm ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	ADD	$1, R2, R3
    
    	//	LADDW rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADD	R1, R2
    
    	//	LADDW imm ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADD	$4, R1
    
    	//	LMUL rreg ',' rreg
    	//	{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
    - Viewed (0)
  8. src/math/tanh_s390x.s

    	FMOVD   0(R1), F2
    	WFCHDBS V0, V2, V4
    	BEQ     L9
    	WFCHDBS V2, V0, V2
    	BNE     L1
    	MOVD    $tanhxmone<>+0(SB), R1
    	FMOVD   0(R1), F0
    	FMOVD   F0, ret+8(FP)
    	RET
    
    L3:
    	FADD    F4, F2
    	FMOVD   tanhrodataL18<>+80(SB), F4
    	FMADD   F4, F2, F0
    	FMOVD   tanhrodataL18<>+72(SB), F1
    	WFMDB   V0, V0, V3
    	FMOVD   tanhrodataL18<>+64(SB), F2
    	WFMADB  V0, V1, V2, V1
    	FMOVD   tanhrodataL18<>+56(SB), F4
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 4.6K bytes
    - Viewed (0)
  9. src/math/cosh_s390x.s

    	WORD    $0xA7487FBE     //lhi %r4,32702
    	FMADD   F3, F2, F1
    	SUBW    R1, R4
    	RISBGZ	$57, $60, $3, R4, R12
    	WORD    $0x682C5000     //ld %f2,0(%r12,%r5)
    	FMSUB   F2, F4, F0
    	RISBGN	$0, $15, $48, R1, R2
    	WFMADB  V0, V6, V2, V6
    	RISBGN	$0, $15, $48, R4, R3
    	LDGR    R2, F2
    	LDGR    R3, F0
    	FMADD   F2, F1, F2
    	FMADD   F0, F6, F0
    	FADD    F2, F0
    	FMOVD   F0, ret+8(FP)
    	RET
    
    L22:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 5.6K bytes
    - Viewed (0)
  10. src/math/sin_s390x.s

    	MOVD    $sincoss2<>+0(SB), R2
    	FMOVD   0(R2), F7
    	WFMADB  V6, V3, V7, V3
    	MOVD    $sincoss3<>+0(SB), R2
    	FMADD   F5, F4, F0
    	FMOVD   0(R2), F4
    	MOVD    $sincoss1<>+0(SB), R2
    	FMADD   F1, F6, F4
    	FMOVD   0(R2), F1
    	FMADD   F3, F2, F1
    	FMUL    F0, F2
    	WFMADB  V6, V4, V1, V6
    	TMLL	R1, $2
    	FMADD   F6, F2, F0
    	BNE     L34
    	FMOVD   F0, ret+8(FP)
    	RET
    
    L33:
    	MOVD    $sincosxnan<>+0(SB), R1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 04:25:54 UTC 2023
    - 8.6K bytes
    - Viewed (0)
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