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Results 1 - 10 of 44 for R2 (0.01 seconds)

  1. src/cmd/asm/internal/asm/testdata/arm64.s

    	FMOVS	F1, 0x44332211(R2)	// FMOVS	F1, 1144201745(R2)
    	FMOVD	F1, 0x1007000(R2)	// FMOVD	F1, 16805888(R2)
    	FMOVD	F1, 0x44332211(R2)	// FMOVD	F1, 1144201745(R2)
    	FMOVQ	F1, 0x1003000(R2)	// FMOVQ	F1, 16789504(R2)
    	FMOVQ	F1, 0x44332211(R2)	// FMOVQ	F1, 1144201745(R2)
    
    	MOVB	0x1000000(R1), R2	// MOVB		16777216(R1), R2
    	MOVB	0x44332211(R1), R2	// MOVB		1144201745(R1), R2
    	MOVH	0x1000000(R1), R2	// MOVH		16777216(R1), R2
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Mon Nov 10 17:34:13 GMT 2025
    - 96.1K bytes
    - Click Count (0)
  2. compat/maven-compat/src/test/java/org/apache/maven/artifact/repository/MavenArtifactRepositoryTest.java

            MavenArtifactRepositorySubclass r2 = new MavenArtifactRepositorySubclass("foo");
            MavenArtifactRepositorySubclass r3 = new MavenArtifactRepositorySubclass("bar");
    
            assertTrue(r1.hashCode() == r2.hashCode());
            assertFalse(r1.hashCode() == r3.hashCode());
    
            assertTrue(r1.equals(r2), "Expected " + r1 + " to equal " + r2);
            assertTrue(r2.equals(r1), "Expected " + r2 + " to equal " + r1);
    
    Created: Sun Dec 28 03:35:09 GMT 2025
    - Last Modified: Wed Sep 17 10:01:14 GMT 2025
    - 2K bytes
    - Click Count (0)
  3. src/cmd/asm/internal/asm/testdata/arm.s

    	AND	R0->R1, R2, R3       // 503102e0
    	AND	R0@>R1, R2, R3       // 703102e0
    	AND.S	R0<<R1, R2, R3       // 103112e0
    	AND.S	R0>>R1, R2, R3       // 303112e0
    	AND.S	R0->R1, R2, R3       // 503112e0
    	AND.S	R0@>R1, R2, R3       // 703112e0
    	AND	R0<<R1, R2           // 102102e0
    	AND	R0>>R1, R2           // 302102e0
    	AND	R0->R1, R2           // 502102e0
    	AND	R0@>R1, R2           // 702102e0
    	AND.S	R0<<R1, R2           // 102112e0
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Fri Dec 15 20:51:01 GMT 2023
    - 69K bytes
    - Click Count (0)
  4. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	//TODO STTRH 9(R10), R19                   // 53990078
    	STXP (R1, R2), (R3), R10                   // 61082ac8
    	STXP (R1, R2), (RSP), R10                  // e10b2ac8
    	STXPW (R1, R2), (R3), R10                  // 61082a88
    	STXPW (R1, R2), (RSP), R10                 // e10b2a88
    	STXRW R2, (R19), R20                       // 627e1488
    	STXR R15, (R21), R13                       // af7e0dc8
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Mon Jul 24 01:11:41 GMT 2023
    - 43.9K bytes
    - Click Count (0)
  5. src/cmd/asm/internal/asm/testdata/ppc64_p10.s

    	SETBC CR2EQ, R2                         // 7c4a0300
    	SETBCR CR2LT, R2                        // 7c480340
    	SETNBC CR2GT, R2                        // 7c490380
    	SETNBCR CR6SO, R2                       // 7c5b03c0
    	STXVP VS6, 12352(R5)                    // 18c53041
    	STXVPX VS22, (R1)(R2)                   // 7ec20b9a
    	STXVRBX VS2, (R1)(R2)                   // 7c42091a
    	STXVRDX VS2, (R1)(R2)                   // 7c4209da
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Thu Mar 23 20:52:57 GMT 2023
    - 14.3K bytes
    - Click Count (0)
  6. .github/workflows/update-rbe.yml

            # TF 2.9
            map sigbuild-r2.9 2.9-python3.9
            map sigbuild-r2.9-python3.8 2.9-python3.8
            map sigbuild-r2.9-python3.9 2.9-python3.9
            map sigbuild-r2.9-python3.10 2.9-python3.10
            # TF 2.10
            map sigbuild-r2.10 2.10-python3.9
            map sigbuild-r2.10-python3.8 2.10-python3.8
            map sigbuild-r2.10-python3.9 2.10-python3.9
            map sigbuild-r2.10-python3.10 2.10-python3.10
            # TF 2.11
    Created: Tue Dec 30 12:39:10 GMT 2025
    - Last Modified: Mon Dec 01 09:57:00 GMT 2025
    - 7.2K bytes
    - Click Count (1)
  7. src/cmd/asm/internal/asm/parse.go

    // register parses a full register reference where there is no symbol present (as in 4(R0) or R(10) but not sym(SB))
    // including forms involving multiple registers such as R1:R2.
    func (p *Parser) register(name string, prefix rune) (r1, r2 int16, scale int8, ok bool) {
    	// R1 or R(1) R1:R2 R1,R2 R1+R2, or R1*scale.
    	r1, ok = p.registerReference(name)
    	if !ok {
    		return
    	}
    	if prefix != 0 && prefix != '*' { // *AX is OK.
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Wed Nov 12 03:59:40 GMT 2025
    - 37.3K bytes
    - Click Count (0)
  8. src/cmd/asm/internal/asm/testdata/armerror.s

    	BFX	$-2, $4, R2, R3    // ERROR "wrong width or LSB"
    	BFXU	$4, R2, R5, R2     // ERROR "missing or wrong LSB"
    	BFXU	$4, R2, R5         // ERROR "missing or wrong LSB"
    	BFC	$12, $8, R2, R3    // ERROR "illegal combination"
    	MOVB	R0>>8, R2          // ERROR "illegal shift"
    	MOVH	R0<<16, R2         // ERROR "illegal shift"
    	MOVBS	R0->8, R2          // ERROR "illegal shift"
    	MOVHS	R0<<24, R2         // ERROR "illegal shift"
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Wed Oct 23 15:18:14 GMT 2024
    - 14.5K bytes
    - Click Count (0)
  9. src/cmd/asm/internal/asm/testdata/mips.s

    	//	}
    	MOVW	R1, R2
    	MOVW	LO, R1
    	MOVW	HI, R1
    	MOVW	R1, LO
    	MOVW	R1, HI
    	MOVW	R1, R2
    	MOVW	LO, R1
    	MOVW	HI, R1
    	MOVW	R1, LO
    	MOVW	R1, HI
    
    	//	LMOVW addr ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	MOVW	foo<>+3(SB), R2
    	MOVW	16(R1), R2
    	MOVW	(R1), R2
    	MOVW	foo<>+3(SB), R2
    	MOVW	16(R1), R2
    	MOVW	(R1), R2
    	LL	(R1), R2
    
    	//	LMOVB rreg ',' rreg
    	//	{
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 6.7K bytes
    - Click Count (0)
  10. src/cmd/asm/internal/asm/testdata/mips64.s

    	JAL	foo(SB) // CALL foo(SB)
    	BEQ	R1, 2(PC)
    	JMP	foo(SB)
    	CALL	foo(SB)
    	RET	foo(SB)
    
    	// unary operation
    	NEGW	R1, R2 // 00011023
    	NEGV	R1, R2 // 0001102f
    
    	WSBH	R1, R2 // 7c0110a0
    	DSBH	R1, R2 // 7c0110a4
    	DSHD	R1, R2 // 7c011164
    
    	SEB	R1, R2 // 7c011420
    	SEH	R1, R2 // 7c011620
    
    	RET
    
    // MSA VMOVI
    	VMOVB	$511, W0   // 7b0ff807
    	VMOVH	$24, W23   // 7b20c5c7
    Created: Tue Dec 30 11:13:12 GMT 2025
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 12.4K bytes
    - Click Count (0)
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