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Results 11 - 20 of 70 for divlu (0.11 sec)

  1. src/cmd/cgo/internal/testcshared/testdata/p/p.go

    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    package p
    
    import "C"
    
    //export FromPkg
    func FromPkg() int32 { return 1024 }
    
    //export Divu
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 12 11:59:56 UTC 2023
    - 299 bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (Div64u x y) => (Select1 (DIVVU x y))
    (Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
    (Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
    (Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
    (Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
    (Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  3. test/fixedbugs/issue19507.dir/div_arm.s

    // Copyright 2017 The Go Authors. All rights reserved.
    // Use of this source code is governed by a BSD-style
    // license that can be found in the LICENSE file.
    
    TEXT ·f(SB),0,$0-8
    	MOVW	x+0(FP), R1
    	MOVW	x+4(FP), R2
    	DIVU	R1, R2
    	DIV	R1, R2
    	MODU	R1, R2
    	MOD	R1, R2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 13 23:44:52 UTC 2018
    - 271 bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (Div64 x y) => (DIVV x y)
    (Div64u ...) => (DIVVU ...)
    (Div32 x y) => (DIVV (SignExt32to64 x) (SignExt32to64 y))
    (Div32u x y) => (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))
    (Div16 x y) => (DIVV (SignExt16to64 x) (SignExt16to64 y))
    (Div16u x y) => (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))
    (Div8 x y) => (DIVV (SignExt8to64 x) (SignExt8to64 y))
    (Div8u x y) => (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))
    (Div(32|64)F ...) => (DIV(F|D) ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/arm/anames.go

    	"FNMULAD",
    	"FMULSF",
    	"FMULSD",
    	"FNMULSF",
    	"FNMULSD",
    	"DIVF",
    	"DIVD",
    	"SQRTF",
    	"SQRTD",
    	"ABSF",
    	"ABSD",
    	"NEGF",
    	"NEGD",
    	"SRL",
    	"SRA",
    	"SLL",
    	"MULU",
    	"DIVU",
    	"MUL",
    	"MMUL",
    	"DIV",
    	"MOD",
    	"MODU",
    	"DIVHW",
    	"DIVUHW",
    	"MOVB",
    	"MOVBS",
    	"MOVBU",
    	"MOVH",
    	"MOVHS",
    	"MOVHU",
    	"MOVW",
    	"MOVM",
    	"SWPBU",
    	"SWPW",
    	"RFE",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 16 15:58:33 UTC 2019
    - 1.4K bytes
    - Viewed (0)
  6. test/codegen/arithmetic.go

    func Pow2DivisibleSigned(n1, n2 int) (bool, bool) {
    	// 386:"TESTL\t[$]63",-"DIVL",-"SHRL"
    	// amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ"
    	// arm:"AND\t[$]63",-".*udiv",-"SRA"
    	// arm64:"TST\t[$]63",-"UDIV",-"ASR",-"AND"
    	// ppc64x:"ANDCC",-"RLDICL",-"SRAD",-"CMP"
    	a := n1%64 == 0 // signed divisible
    
    	// 386:"TESTL\t[$]63",-"DIVL",-"SHRL"
    	// amd64:"TESTQ\t[$]63",-"DIVQ",-"SHRQ"
    	// arm:"AND\t[$]63",-".*udiv",-"SRA"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 15:28:00 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (Mul32uhilo ...) => (MULTU ...)
    
    (Div32 x y) => (Select1 (DIV x y))
    (Div32u x y) => (Select1 (DIVU x y))
    (Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
    (Div16u x y) => (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
    (Div8 x y) => (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y)))
    (Div8u x y) => (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y)))
    (Div(32|64)F ...) => (DIV(F|D) ...)
    
    (Mod32 x y) => (Select0 (DIV x y))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/riscv/anames.go

    	"PAUSE",
    	"ADDIW",
    	"SLLIW",
    	"SRLIW",
    	"SRAIW",
    	"ADDW",
    	"SLLW",
    	"SRLW",
    	"SUBW",
    	"SRAW",
    	"LD",
    	"SD",
    	"MUL",
    	"MULH",
    	"MULHU",
    	"MULHSU",
    	"MULW",
    	"DIV",
    	"DIVU",
    	"REM",
    	"REMU",
    	"DIVW",
    	"DIVUW",
    	"REMW",
    	"REMUW",
    	"LRD",
    	"SCD",
    	"LRW",
    	"SCW",
    	"AMOSWAPD",
    	"AMOADDD",
    	"AMOANDD",
    	"AMOORD",
    	"AMOXORD",
    	"AMOMAXD",
    	"AMOMAXUD",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  9. src/runtime/time_windows_386.s

    	SBBL $(delta >> 32), DX
    
    	// nano/100 = DX:AX
    	// split into two decimal halves by div 1e9.
    	// (decimal point is two spots over from correct place,
    	// but we avoid overflow in the high word.)
    	MOVL	$1000000000, CX
    	DIVL	CX
    	MOVL	AX, DI
    	MOVL	DX, SI
    
    	// DI = nano/100/1e9 = nano/1e11 = sec/100, DX = SI = nano/100%1e9
    	// split DX into seconds and nanoseconds by div 1e7 magic multiply.
    	MOVL	DX, AX
    	MOVL	$1801439851, CX
    	MULL	CX
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Sep 07 17:19:45 UTC 2023
    - 1.7K bytes
    - Viewed (0)
  10. src/runtime/vlop_386.s

    	ADDL	AX, BX
    	ADCL	$0, DX
    	MOVL	BX, 4(CX)
    	MOVL	DX, AX
    	MOVL	AX, hi32+16(FP)
    	RET
    
    TEXT runtime·_div64by32(SB), NOSPLIT, $0
    	MOVL	r+12(FP), CX
    	MOVL	a_lo+0(FP), AX
    	MOVL	a_hi+4(FP), DX
    	DIVL	b+8(FP)
    	MOVL	DX, 0(CX)
    	MOVL	AX, q+16(FP)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jun 04 07:25:06 UTC 2020
    - 2K bytes
    - Viewed (0)
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