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Results 11 - 20 of 21 for asyncPreempt2 (0.26 sec)
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src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
"F15", "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", // If you add registers, update asyncPreempt in runtime. // pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNamesLOONG64) > 64 { panic("too many registers") }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
"F23", "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", "HI", // high bits of multiplication "LO", // low bits of multiplication // If you add registers, update asyncPreempt in runtime. // pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNamesMIPS64) > 64 { panic("too many registers") }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
"F14", "F16", "F18", "F20", "F22", "F24", "F26", "F28", "F30", "HI", // high bits of multiplication "LO", // low bits of multiplication // If you add registers, update asyncPreempt in runtime. // pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNamesMIPS) > 64 { panic("too many registers") } num := map[string]int{}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/runtime/proc_test.go
} func TestAsyncPreempt(t *testing.T) { if !runtime.PreemptMSupported { t.Skip("asynchronous preemption not supported on this platform") } output := runTestProg(t, "testprog", "AsyncPreempt") want := "OK\n" if output != want { t.Fatalf("want %s, got %s\n", want, output) } } func TestGCFairness(t *testing.T) { output := runTestProg(t, "testprog", "GCFairness") want := "OK\n"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 25.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/386Ops.go
var regNames386 = []string{ "AX", "CX", "DX", "BX", "SP", "BP", "SI", "DI", "X0", "X1", "X2", "X3", "X4", "X5", "X6", "X7", // If you add registers, update asyncPreempt in runtime // pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNames386) > 64 { panic("too many registers") } num := map[string]int{}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 14 08:10:32 UTC 2023 - 45.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
"F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", // tmp // If you add registers, update asyncPreempt in runtime. // pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNamesARM) > 64 { panic("too many registers") } num := map[string]int{}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
"F23", "F24", "F25", "F26", "F27", "F28", "F29", "F30", // "F31", the allocator is limited to 64 entries. We sacrifice this FPR to support XER. "XER", // If you add registers, update asyncPreempt in runtime. // "CR0", // "CR1", // "CR2", // "CR3", // "CR4", // "CR5", // "CR6", // "CR7", // "CR", // "LR", // "CTR", } func init() {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/S390XOps.go
"SP", // R15 "F0", "F1", "F2", "F3", "F4", "F5", "F6", "F7", "F8", "F9", "F10", "F11", "F12", "F13", "F14", "F15", // If you add registers, update asyncPreempt in runtime. //pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNamesS390X) > 64 { panic("too many registers") } num := map[string]int{}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 52.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
"F15", "F16", "F17", "F18", "F19", "F20", "F21", "F22", "F23", "F24", "F25", "F26", "F27", "F28", "F29", "F30", "F31", // If you add registers, update asyncPreempt in runtime. // pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNamesARM64) > 64 { panic("too many registers") }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
"X1", "X2", "X3", "X4", "X5", "X6", "X7", "X8", "X9", "X10", "X11", "X12", "X13", "X14", "X15", // constant 0 in ABIInternal // If you add registers, update asyncPreempt in runtime // pseudo-registers "SB", } func init() { // Make map from reg names to reg integers. if len(regNamesAMD64) > 64 { panic("too many registers") } num := map[string]int{}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1)