xergp       = regInfo{inputs: []regMask{xer}, outputs: []regMask{gp}, clobbers: xer}
		gp11cxer    = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}, clobbers: xer}
		gp11xer     = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp, xer}}
		gp1xer1xer  = regInfo{inputs: []regMask{gp | sp | sb, xer}, outputs: []regMask{gp, xer}, clobbers: xer}

func (c *sigctxt) trap() uint64 { return c.regs().trap }
func (c *sigctxt) ctr() uint64  { return c.regs().ctr }
func (c *sigctxt) link() uint64 { return c.regs().link }
func (c *sigctxt) xer() uint64  { return c.regs().xer }
func (c *sigctxt) ccr() uint64  { return c.regs().ccr }

func (c *sigctxt) sigcode() uint32 { return uint32(c.info.si_code) }
func (c *sigctxt) sigaddr() uint64 { return c.info.si_addr }

	MOVD R22, 176(R1)
	MOVD R23, 184(R1)
	MOVD R24, 192(R1)
	MOVD R25, 200(R1)
	MOVD R26, 208(R1)
	MOVD R27, 216(R1)
	MOVD R28, 224(R1)
	MOVD R29, 232(R1)
	MOVW CR, R31
	MOVW R31, 240(R1)
	MOVD XER, R31
	MOVD R31, 248(R1)
	FMOVD F0, 256(R1)
	FMOVD F1, 264(R1)
	FMOVD F2, 272(R1)
	FMOVD F3, 280(R1)
	FMOVD F4, 288(R1)
	FMOVD F5, 296(R1)
	FMOVD F6, 304(R1)
	FMOVD F7, 312(R1)
	FMOVD F8, 320(R1)

//go:nowritebarrierrec
func (c *sigctxt) pc() uint64 { return c.regs().iar }

func (c *sigctxt) ctr() uint64    { return c.regs().ctr }
func (c *sigctxt) link() uint64   { return c.regs().lr }
func (c *sigctxt) xer() uint32    { return c.regs().xer }
func (c *sigctxt) ccr() uint32    { return c.regs().cr }
func (c *sigctxt) fpscr() uint32  { return c.regs().fpscr }
func (c *sigctxt) fpscrx() uint32 { return c.regs().fpscrx }

	print("r30  ", hex(c.r30()), "\t")
	print("r31  ", hex(c.r31()), "\n")
	print("pc   ", hex(c.pc()), "\t")
	print("ctr  ", hex(c.ctr()), "\n")
	print("link ", hex(c.link()), "\t")
	print("xer  ", hex(c.xer()), "\n")
	print("ccr  ", hex(c.ccr()), "\t")
	print("trap ", hex(c.trap()), "\n")
}

//go:nosplit
//go:nowritebarrierrec
func (c *sigctxt) sigpc() uintptr    { return uintptr(c.pc()) }

	__extctx_magic int32
	__pad          int32
}

type context64 struct {
	gpr        [32]uint64
	msr        uint64
	iar        uint64
	lr         uint64
	ctr        uint64
	cr         uint32
	xer        uint32
	fpscr      uint32
	fpscrx     uint32
	except     [1]uint64
	fpr        [32]float64
	fpeu       uint8
	fpinfo     uint8
	fpscr24_31 uint8
	pad        [1]uint8
	excp_type  int32
}

	_O_CLOEXEC   = 0x80000
	_SA_RESTORER = 0
)

type ptregs struct {
	gpr       [32]uint64
	nip       uint64
	msr       uint64
	orig_gpr3 uint64
	ctr       uint64
	link      uint64
	xer       uint64
	ccr       uint64
	softe     uint64
	trap      uint64
	dar       uint64
	dsisr     uint64
	result    uint64
}

type vreg struct {
	u [4]uint32
}

type stackt struct {

	_O_CLOEXEC   = 0x80000
	_SA_RESTORER = 0
)

type ptregs struct {
	gpr       [32]uint64
	nip       uint64
	msr       uint64
	orig_gpr3 uint64
	ctr       uint64
	link      uint64
	xer       uint64
	ccr       uint64
	softe     uint64
	trap      uint64
	dar       uint64
	dsisr     uint64
	result    uint64
}

type vreg struct {
	u [4]uint32
}

type stackt struct {

			}
		}

	case "mtspr":
		opcode := inst.Op.String()
		buf.WriteString(opcode[0:2])
		switch spr := inst.Args[0].(type) {
		case SpReg:
			switch spr {
			case 1:
				buf.WriteString("xer")
				startArg = 1
			case 8:
				buf.WriteString("lr")
				startArg = 1
			case 9:
				buf.WriteString("ctr")
				startArg = 1
			default:
				buf.WriteString("spr")
			}
		default:

	}
	if REG_A0 <= r && r <= REG_A7 {
		return fmt.Sprintf("A%d", r-REG_A0)
	}
	if r == REG_CR {
		return "CR"
	}
	if REG_SPR0 <= r && r <= REG_SPR0+1023 {
		switch r {
		case REG_XER:
			return "XER"

		case REG_LR:
			return "LR"

		case REG_CTR:
			return "CTR"
		}

		return fmt.Sprintf("SPR(%d)", r-REG_SPR0)
	}

	if r == REG_FPSCR {
		return "FPSCR"
	}
	if r == REG_MSR {