VPGATHERDQ X2, 664(X2*8), X7    // ERROR "mask, index, and destination registers should be distinct"
	VPGATHERDQ X2, 664(X7*8), X2    // ERROR "mask, index, and destination registers should be distinct"
	VPGATHERDQ X7, 664(X2*8), X2    // ERROR "mask, index, and destination registers should be distinct"
	// Non-X0 for Yxr0 should produce an error

		// Test AVX512 suffixes.
		{"VADDPD.A X0, X1, X2", `unknown suffix "A"`},
		{"VADDPD.A.A X0, X1, X2", `unknown suffix "A"; duplicate suffix "A"`},
		{"VADDPD.A.A.A X0, X1, X2", `unknown suffix "A"; duplicate suffix "A"`},
		{"VADDPD.A.B X0, X1, X2", `unknown suffix "A"; unknown suffix "B"`},
		{"VADDPD.Z.A X0, X1, X2", `Z suffix should be the last; unknown suffix "A"`},
		{"VADDPD.Z.Z X0, X1, X2", `Z suffix should be the last; duplicate suffix "Z"`},

	ADDSD (R11), X2                         // f2410f5813
	ADDSD X2, X2                            // f20f58d2
	ADDSD X11, X2                           // f2410f58d3
	ADDSD (BX), X11                         // f2440f581b
	ADDSD (R11), X11                        // f2450f581b
	ADDSD X2, X11                           // f2440f58da
	ADDSD X11, X11                          // f2450f58db

	XVSRLB		$7, X2, X1	// 413c3077
	XVSRLB		$5, X2		// 42343077
	XVSRLH		$0, X2, X1	// 41403077
	XVSRLH		$15, X2, X1	// 417c3077
	XVSRLH		$9, X2		// 42643077
	XVSRLW		$0, X2, X1	// 41803077
	XVSRLW		$31, X2, X1	// 41fc3077
	XVSRLW		$14, X2		// 42b83077
	XVSRLV		$0, X2, X1	// 41003177
	XVSRLV		$63, X2, X1	// 41fc3177
	XVSRLV		$45, X2		// 42b43177
	XVSRAB		$0, X2, X1	// 41203477
	XVSRAB		$7, X2, X1	// 413c3477

	SHA256MSG1 X2, X2        // 0f38ccd2
	SHA256MSG1 X11, X2       // 410f38ccd3
	SHA256MSG1 (BX), X11     // 440f38cc1b
	SHA256MSG1 (R11), X11    // 450f38cc1b
	SHA256MSG1 X2, X11       // 440f38ccda
	SHA256MSG1 X11, X11      // 450f38ccdb
	SHA256MSG2 (BX), X2      // 0f38cd13
	SHA256MSG2 (R11), X2     // 410f38cd13
	SHA256MSG2 X2, X2        // 0f38cdd2
	SHA256MSG2 X11, X2       // 410f38cdd3

	IMULB	DX
	IMULW	DX, BX
	IMULL	R11, R12
	IMULQ	foo+4(SB), R11

// LTYPEXC spec8	{ outcode($1, &$2); }
	CMPPD	X1, X2, 4
	CMPPD	foo+4(SB), X2, 4

// LTYPEX spec9	{ outcode($1, &$2); }
	PINSRW	$4, AX, X2
	PINSRW	$4, foo+4(SB), X2

// LTYPERT spec10	{ outcode($1, &$2); }
	JCS	2(PC)
	RETFL	$4

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:

	f1 T1
	f2 T2
}

func NewPair[T1 interface{ M() }, T2 ~int](v1 T1, v2 T2) Pair[T1, T2] {
	return Pair[T1, T2]{f1: v1, f2: v2}
}

func (p Pair[X1, _]) First() X1 {
	return p.f1
}

func (p Pair[_, X2]) Second() X2 {
	return p.f2
}

// Deprecated: Use something else.
func Clone[S ~[]T, T any](s S) S {
	return append(S(nil), s...)

   * @throws X1 when the given throwable is of the declared type X1
   * @throws X2 when the given throwable is of the declared type X2
   */
  public <X1 extends Exception, X2 extends Exception> RuntimeException rethrow(
      Throwable e, Class<X1> declaredType1, Class<X2> declaredType2) throws IOException, X1, X2 {
    checkNotNull(e);
    thrown = e;
    throwIfInstanceOf(e, IOException.class);

PSHUFB X0, X1 ADDQ $0x01, SI ADCQ $0x00, DI MOVQ SI, X2 PINSRQ $0x01, DI, X2 PSHUFB X0, X2 MOVUPS (CX), X0 PXOR X0, X1 PXOR X0, X2 ADDQ $0x10, CX SUBQ $0x0c, AX JE enc192 JB enc128 MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 ADDQ $0x20, CX enc192: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 MOVUPS...

      buf[bufLen++] = getChar(h);

      int x0 = buf[bufLen - 1] & 0xff;
      int x1 = buf[bufLen - 2] & 0xff;
      int x2 = buf[bufLen - 3] & 0xff;
      int x3 = buf[bufLen / 2] & 0xff;
      buf[((x0 << 16) + (x1 << 8) + x2) % bufLen] ^= x3;
      buf[((x1 << 16) + (x2 << 8) + x3) % bufLen] ^= i % 256;
    }
    assertEquals(0x7a1d67c50ec7e167L, h);
  }

  private static long remix(long h) {