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Results 1 - 10 of 24 for F1 (0.04 sec)
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src/cmd/asm/internal/asm/testdata/armerror.s
FMULAD F0, F1 // ERROR "illegal combination" FMULAF F0, F1 // ERROR "illegal combination" FMULSD F0, F1 // ERROR "illegal combination" FMULSF F0, F1 // ERROR "illegal combination" FNMULAD F0, F1 // ERROR "illegal combination" FNMULAF F0, F1 // ERROR "illegal combination" FNMULSD F0, F1 // ERROR "illegal combination"
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 14.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/armv6.s
FNMULSD F5, F6, F7 // 057b96ee DIVF F0, F1, F2 // 002a81ee DIVD.EQ F3, F4, F5 // 035b840e DIVF.NE F0, F2 // 002a821e DIVD F3, F5 // 035b85ee NEGF F0, F1 // 401ab1ee NEGD F4, F5 // 445bb1ee ABSF F0, F1 // c01ab0ee ABSD F4, F5 // c45bb0ee SQRTF F0, F1 // c01ab1ee SQRTD F4, F5 // c45bb1ee MOVFD F0, F1 // c01ab7ee MOVDF F4, F5 // c45bb7ee
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Oct 23 15:18:14 UTC 2024 - 4.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// outcode(int($1), &$2, 0, &$4); // } ABSD F1, F2 // LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD // WORD $1
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 6.7K bytes - Viewed (0) -
src/cmd/api/testdata/src/pkg/p4/p4.go
// license that can be found in the LICENSE file. package p4 type Pair[T1 interface{ M() }, T2 ~int] struct { f1 T1 f2 T2 } func NewPair[T1 interface{ M() }, T2 ~int](v1 T1, v2 T2) Pair[T1, T2] { return Pair[T1, T2]{f1: v1, f2: v2} } func (p Pair[X1, _]) First() X1 { return p.f1 } func (p Pair[_, X2]) Second() X2 { return p.f2 } // Deprecated: Use something else.
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Fri Dec 02 16:29:41 UTC 2022 - 552 bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
FNMSUBS F1, F2, F3, F4 // ec8110fc FNMSUBSCC F1, F2, F3, F4 // ec8110fd FSEL F1, F2, F3, F4 // fc8110ee FSELCC F1, F2, F3, F4 // fc8110ef FABS F1, F2 // fc400a10 FNABS F1, F2 // fc400910 FABSCC F1, F2 // fc400a11 FNABSCC F1, F2 // fc400911 FNEG F1, F2 // fc400850
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Nov 21 18:27:17 UTC 2024 - 51.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
FIEBR $0, F0, F1 // b3570010 FIDBR $7, F2, F3 // b35f7032 FMADD F1, F1, F1 // b31e1011 FMADDS F1, F2, F3 // b30e3012 FMSUB F4, F5, F5 // b31f5045 FMSUBS F6, F6, F7 // b30f7066 LCDBR F0, F2 // b3130020 LPDFR F1, F2 // b3700021 LNDFR F3, F4 // b3710043
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Jul 30 19:29:15 UTC 2025 - 22.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
FLDPD 11(RSP), (F1, F2) // fb2f0091610b406d FLDPD 1024(RSP), (F1, F2) // fb031091610b406d FLDPD.W 8(RSP), (F1, F2) // e18bc06d FLDPD.P 8(RSP), (F1, F2) // e18bc06c FLDPD -31(R0), (F1, F2) // 1b7c00d1610b406d FLDPD -4(R0), (F1, F2) // 1b1000d1610b406d FLDPD -8(R0), (F1, F2) // 01887f6d FLDPD x(SB), (F1, F2) FLDPD x+8(SB), (F1, F2) FLDPS -5(R0), (F1, F2) // 1b1400d1610b402d
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed Mar 26 10:48:50 UTC 2025 - 95.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, 0, &$4); // } ABSD F1, F2 // LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD //Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 08 12:17:12 UTC 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
FCVTDLU X5, F0 // 538032d2 FCVTSD F0, F1 // d3001040 FCVTDS F0, F1 // d3000042 FSGNJD F1, F0, F2 // 53011022 FSGNJND F1, F0, F2 // 53111022 FSGNJXD F1, F0, F2 // 53211022 FMVXD F0, X5 // d30200e2 FMVDX X5, F0 // 538002f2 FMADDD F1, F2, F3, F4 // 4382201a FMSUBD F1, F2, F3, F4 // 4782201a FNMSUBD F1, F2, F3, F4 // 4b82201a FNMADDD F1, F2, F3, F4 // 4f82201a
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Wed May 21 14:19:19 UTC 2025 - 49.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
FCLASSF F4, F5 // 85341401 FCLASSD F4, F5 // 85381401 FFINTFW F0, F1 // 01101d01 FFINTFV F0, F1 // 01181d01 FFINTDW F0, F1 // 01201d01 FFINTDV F0, F1 // 01281d01 FTINTWF F0, F1 // 01041b01 FTINTWD F0, F1 // 01081b01 FTINTVF F0, F1 // 01241b01 FTINTVD F0, F1 // 01281b01 FMAXAF F4, F5, F6 // a6900c01 FMAXAF F4, F5 // a5900c01
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Sep 04 19:24:25 UTC 2025 - 35.5K bytes - Viewed (0)