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Results 1 - 10 of 86 for X6 (0.02 sec)
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src/cmd/asm/internal/asm/testdata/riscv64.s
BGEU X5, X6, 2(PC) // 63f46200 // 2.6: Load and Store Instructions LW (X5), X6 // 03a30200 LW 4(X5), X6 // 03a34200 LWU (X5), X6 // 03e30200 LWU 4(X5), X6 // 03e34200 LH (X5), X6 // 03930200 LH 4(X5), X6 // 03934200 LHU (X5), X6 // 03d30200 LHU 4(X5), X6 // 03d34200 LB (X5), X6 // 03830200 LB 4(X5), X6 // 03834200 LBU (X5), X6 // 03c30200
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/testdata/testbranch/branch_test.s
MOV b+8(FP), X6 MOV $1, X7 BGEU X5, X6, b MOV $0, X7 b: MOV X7, r+16(FP) RET // func testBGEZ(a int64) (r bool) TEXT ·testBGEZ(SB),NOSPLIT,$0-9 MOV a+0(FP), X5 MOV $1, X6 BGEZ X5, b MOV $0, X6 b: MOV X6, r+8(FP) RET // func testBGT(a, b int64) (r bool) TEXT ·testBGT(SB),NOSPLIT,$0-17 MOV a+0(FP), X5 MOV b+8(FP), X6 MOV $1, X7 BGT X5, X6, b MOV $0, X7 b:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Feb 28 21:56:43 UTC 2022 - 2.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64error.s
RORIW $32, X5, X6 // ERROR "immediate out of range 0 to 31" SLLIW $32, X5, X6 // ERROR "immediate out of range 0 to 31" SRLIW $32, X5, X6 // ERROR "immediate out of range 0 to 31" SRAIW $32, X5, X6 // ERROR "immediate out of range 0 to 31" RORIW $-1, X5, X6 // ERROR "immediate out of range 0 to 31" SLLIW $-1, X5, X6 // ERROR "immediate out of range 0 to 31"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 2.8K bytes - Viewed (0) -
src/internal/bytealg/compare_riscv64.s
cmp1a: SLTU X9, X8, X5 SLTU X8, X9, X6 JMP cmp_ret cmp1b: SLTU X16, X15, X5 SLTU X15, X16, X6 JMP cmp_ret cmp1c: SLTU X18, X17, X5 SLTU X17, X18, X6 JMP cmp_ret cmp1d: SLTU X20, X19, X5 SLTU X19, X20, X6 JMP cmp_ret cmp1e: SLTU X22, X21, X5 SLTU X21, X22, X6 JMP cmp_ret cmp1f: SLTU X24, X23, X5 SLTU X23, X24, X6 JMP cmp_ret cmp1g:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 09 13:57:06 UTC 2023 - 3.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512er.s
VRSQRT28SD X8, X6, K1, X6 // 62d2cd09cdf0 or 62d2cd29cdf0 or 62d2cd49cdf0 VRSQRT28SD X6, X6, K1, X6 // 62f2cd09cdf6 or 62f2cd29cdf6 or 62f2cd49cdf6 VRSQRT28SD X0, X6, K1, X6 // 62f2cd09cdf0 or 62f2cd29cdf0 or 62f2cd49cdf0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 28.4K bytes - Viewed (0) -
src/crypto/sha512/sha512block_riscv64.s
MOV (((index-16)&0xf)*8)(X19), X21; \ ROR $19, X5, X7; \ ROR $61, X5, X8; \ SRL $6, X5; \ XOR X7, X5; \ XOR X8, X5; \ ADD X9, X5; \ ROR $1, X6, X7; \ ROR $8, X6, X8; \ SRL $7, X6; \ XOR X7, X6; \ XOR X8, X6; \ ADD X6, X5; \ ADD X21, X5; \ MOV X5, ((index&0xf)*8)(X19) // Calculate T1 in X5. // h is also used as an accumulator. Wt is passed in X5. // T1 = h + BIGSIGMA1(e) + Ch(e, f, g) + Kt + Wt
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 07 14:57:07 UTC 2024 - 9.1K bytes - Viewed (0) -
src/math/floor_riscv64.s
/* whether x is NaN */; \ FEQD F0, F0, X6; \ BNEZ X6, 3(PC); \ /* return NaN if x is NaN */; \ MOVD F0, ret+8(FP); \ RET; \ MOV $PosInf, X6; \ FMVDX X6, F1; \ FABSD F0, F2; \ /* if abs(x) > +Inf, return Inf instead of round(x) */; \ FLTD F1, F2, X6; \ /* Inf should keep same signed with x then return */; \ BEQZ X6, 3(PC); \ FCVTLD.MODE F0, X6; \ FCVTDL X6, F1; \
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 23 08:34:12 UTC 2024 - 1K bytes - Viewed (0) -
src/math/log_amd64.s
// t1 := s2 * (L1 + s4*(L3+s4*(L5+s4*L7))) MOVSD $L7, X6 MULSD X5, X6 ADDSD $L5, X6 MULSD X5, X6 ADDSD $L3, X6 MULSD X5, X6 ADDSD $L1, X6 MULSD X6, X4 // x1= k, x2= f, x3= s, x4= t1, x5= s4 // t2 := s4 * (L2 + s4*(L4+s4*L6)) MOVSD $L6, X6 MULSD X5, X6 ADDSD $L4, X6 MULSD X5, X6 ADDSD $L2, X6 MULSD X6, X5 // x1= k, x2= f, x3= s, x4= t1, x5= t2 // R := t1 + t2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Mar 23 20:52:57 UTC 2023 - 3.7K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/asm_test.go
asm := ` TEXT _stub(SB),$0-0 LB 4096(X5), X6 LH 4096(X5), X6 LW 4096(X5), X6 LD 4096(X5), X6 LBU 4096(X5), X6 LHU 4096(X5), X6 LWU 4096(X5), X6 SB X6, 4096(X5) SH X6, 4096(X5) SW X6, 4096(X5) SD X6, 4096(X5) FLW 4096(X5), F6 FLD 4096(X5), F6 FSW F6, 4096(X5) FSD F6, 4096(X5) MOVB 4096(X5), X6 MOVH 4096(X5), X6 MOVW 4096(X5), X6 MOV 4096(X5), X6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 01:50:18 UTC 2023 - 7.9K bytes - Viewed (0) -
src/crypto/internal/bigmod/nat_riscv64.s
ADD X9, X22, X29 // next c MULHU X11, X6, X12 // z_hi[1] = x[1] * y MUL X11, X6, X11 // z_lo[1] = x[1] * y ADD X11, X13, X21 // z_lo[1] = x[1] * y + z[1] SLTU X11, X21, X22 ADD X12, X22, X12 // z_hi[1] = x[1] * y + z[1] ADD X21, X29, X13 // z_lo[1] = x[1] * y + z[1] + c SLTU X21, X13, X22 ADD X12, X22, X29 // next c MULHU X14, X6, X15 // z_hi[2] = x[2] * y MUL X14, X6, X14 // z_lo[2] = x[2] * y
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Nov 09 13:57:06 UTC 2023 - 2.2K bytes - Viewed (0)