BigInteger plusHalfSquared = result.pow(2).add(result).shiftLeft(2).add(ONE);
      BigInteger x4 = x.shiftLeft(2);
      // sqrt(x) < result + 0.5, so 4 * x < (result + 0.5)^2 * 4
      // (result + 0.5)^2 * 4 = (result^2 + result)*4 + 1
      assertTrue(x4.compareTo(plusHalfSquared) < 0);
      BigInteger minusHalfSquared = result.pow(2).subtract(result).shiftLeft(2).add(ONE);

	VPGATHERDQ Y0, 8(X4*1), Y6              // c4e2fd90342508000000
	VPGATHERDQ Y0, -8(X4*1), Y6             // c4e2fd903425f8ffffff
	VPGATHERDQ Y0, 0(X4*1), Y6              // c4e2fd90342500000000
	VPGATHERDQ Y0, 664(X4*1), Y6            // c4e2fd90342598020000
	VPGATHERDQ Y0, 8(X4*8), Y6              // c4e2fd9034e508000000
	VPGATHERDQ Y0, -8(X4*8), Y6             // c4e2fd9034e5f8ffffff

	V4FNMADDPS 99(R15)(R15*1), [Z21-Z24], K3, Z12      // 62125743aaa43f63000000
	V4FNMADDPS (DX), [Z21-Z24], K3, Z12                // 62725743aa22
	V4FNMADDSS -17(BP)(SI*8), [X1-X4], K4, X11         // 6272770cab9cf5efffffff or 6272772cab9cf5efffffff or 6272774cab9cf5efffffff
	V4FNMADDSS (R15), [X1-X4], K4, X11                 // 6252770cab1f or 6252772cab1f or 6252774cab1f

	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},
	{"X8", "X8"},
	{"X9", "X9"},
	{"_expand_key_128<>(SB)", "_expand_key_128<>(SB)"},
	{"_seek<>(SB)", "_seek<>(SB)"},
	{"a2+16(FP)", "a2+16(FP)"},

	VSEQV		V1, V2, V3      // 43840170
	XVSEQB		X3, X2, X4      // 440c0074
	XVSEQH		X3, X2, X4      // 448c0074
	XVSEQW		X3, X2, X4      // 440c0174
	XVSEQV		X3, X2, X4      // 448c0174
	VSEQB		$0, V2, V3      // 43008072
	VSEQH		$1,  V2, V3     // 43848072
	VSEQW		$8, V2, V3      // 43208172
	VSEQV		$15, V2, V3     // 43bc8172
	VSEQV		$-15, V2, V3    // 43c48172
	XVSEQB		$0, X2, X4      // 44008076
	XVSEQH		$3, X2, X4      // 448c8076

// in the usual way by the opcode itself. Asm must use AMRC for both instructions, so
// we return the opcode for MRC so that asm doesn't need to import obj/arm.
func ARMMRCOffset(op obj.As, cond string, x0, x1, x2, x3, x4, x5 int64) (offset int64, op0 obj.As, ok bool) {
	op1 := int64(0)
	if op == arm.AMRC {
		op1 = 1
	}
	bits, ok := ParseARMCondition(cond)
	if !ok {
		return
	}
	offset = (0xe << 24) | // opcode

_expand_key_128<>() // Requires: SSE, SSE2 TEXT _expand_key_128<>(SB), NOSPLIT, $0 PSHUFD $0xff, X1, X1 SHUFPS $0x10, X0, X4 PXOR X4, X0 SHUFPS $0x8c, X0, X4 PXOR X4, X0 PXOR X1, X0 MOVUPS X0, (BX) ADDQ $0x10, BX RET // func _expand_key_192a<>() // Requires: SSE, SSE2 TEXT _expand_key_192a<>(SB), NOSPLIT, $0 PSHUFD $0x55, X1, X1 SHUFPS $0x10, X0, X4 PXOR X4, X0 SHUFPS $0x8c, X0, X4 PXOR X4, X0 PXOR X1, X0 MOVAPS X2, X5 MOVAPS X2, X6 PSLLDQ $0x04, X5 PSHUFD $0xff, X0, X3 PXOR X3, X2 PXOR X5, X2 MOVAPS X0,...

	VGATHERDPD (AX)(X4*1), K3, X6                      // 62f2fd0b923420
	VGATHERDPD (BP)(X10*2), K3, X6                     // 62b2fd0b92745500
	VGATHERDPD (R10)(X29*8), K3, X6                    // 6292fd039234ea
	VGATHERDPD (DX)(X10*4), K7, Y22                    // 62a2fd2f923492
	VGATHERDPD (SP)(X4*2), K7, Y22                     // 62e2fd2f923464

			x2 := int64(p.getRegister(prog, op, &a[2]))
			x3 := int64(p.getRegister(prog, op, &a[3]))
			x4 := int64(p.getRegister(prog, op, &a[4]))
			x5 := p.getConstant(prog, op, &a[5])
			// Cond is handled specially for this instruction.
			offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5)
			if !ok {
				p.errorf("unrecognized condition code .%q", cond)
			}
			prog.To.Offset = offset

    }
    return retVal;
  }

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,