VLSE8V		(X10), X10, X11			// ERROR "expected vector register in vd position"
	VLSE8V		(V1), X10, V3			// ERROR "expected integer register in rs1 position"
	VLSE8V		(X10), V1, V0, V3		// ERROR "expected integer register in rs2 position"
	VSSE8V		V3, (X10)			// ERROR "expected integer register in rs2 position"
	VSSE8V		X10, X11, (X10)			// ERROR "expected vector register in vd position"
	VSSE8V		V3, X11, (V1)			// ERROR "expected integer register in rs1 position"

	VL2RE32V	(X10), V2			// 07618522
	VL2RE64V	(X10), V2			// 07718522
	VL4RV		(X10), V4			// 07028562
	VL4RE8V		(X10), V4			// 07028562
	VL4RE16V	(X10), V4			// 07528562
	VL4RE32V	(X10), V4			// 07628562
	VL4RE64V	(X10), V4			// 07728562
	VL8RV		(X10), V8			// 070485e2
	VL8RE8V		(X10), V8			// 070485e2
	VL8RE16V	(X10), V8			// 075485e2
	VL8RE32V	(X10), V8			// 076485e2
	VL8RE64V	(X10), V8			// 077485e2

	//
	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"
	VLSE8V		(X10), X10, V1, V3		// ERROR "invalid vector mask register"
	VSSE8V		V3, X11, V1, (X10)		// ERROR "invalid vector mask register"
	VLUXEI8V	(X10), V2, V1, V3		// ERROR "invalid vector mask register"

	VADDPD (AX), X29, X28       // 626195005820
	VADDPD (AX), X29, X10       // 627195005810
	VADDPD (AX), X10, X28       // 6261ad085820
	VADDPD (CX)(AX*1), X29, X0  // 62f19500580401
	VADDPD (CX)(AX*1), X1, X28  // 6261f508582401
	VADDPD (CX)(AX*1), X29, X28 // 62619500582401
	VADDPD (CX)(AX*1), X29, X10 // 62719500581401
	VADDPD (CX)(AX*1), X10, X28 // 6261ad08582401
	VADDPD (CX)(AX*2), X29, X0  // 62f19500580441

	V4FMADDSS (DI), [X0-X3], K5, X22                   // 62e27f0d9b37 or 62e27f2d9b37 or 62e27f4d9b37
	V4FMADDSS 7(AX), [X10-X13], K5, X22                // 62e22f0d9bb007000000 or 62e22f2d9bb007000000 or 62e22f4d9bb007000000
	V4FMADDSS (DI), [X10-X13], K5, X22                 // 62e22f0d9b37 or 62e22f2d9b37 or 62e22f4d9b37

X10, X11, X12, X13, X14) SHA256ROUND0(4, X14, X15, X16, X17, X10, X11, X12, X13) SHA256ROUND0(5, X13, X14, X15, X16, X17, X10, X11, X12) SHA256ROUND0(6, X12, X13, X14, X15, X16, X17, X10, X11) SHA256ROUND0(7, X11, X12, X13, X14, X15, X16, X17, X10) SHA256ROUND0(8, X10, X11, X12, X13, X14, X15, X16, X17) SHA256ROUND0(9, X17, X10, X11, X12, X13, X14, X15, X16) SHA256ROUND0(10, X16, X17, X10, X11, X12, X13, X14, X15) SHA256ROUND0(11, X15, X16, X17, X10, X11, X12, X13, X14) SHA256ROUND0(12, X14, X15,...

	{"R12", "R12"},
	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"g", "R14"},
	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},

	VGATHERDPD (AX)(X4*1), K3, X6                      // 62f2fd0b923420
	VGATHERDPD (BP)(X10*2), K3, X6                     // 62b2fd0b92745500
	VGATHERDPD (R10)(X29*8), K3, X6                    // 6292fd039234ea
	VGATHERDPD (DX)(X10*4), K7, Y22                    // 62a2fd2f923492
	VGATHERDPD (SP)(X4*2), K7, Y22                     // 62e2fd2f923464

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,
    X24,
    X25,
    X26,
    X27,

	XVMOVQ		R7, X9.W[2]     // e9c8eb76
	XVMOVQ		R8, X10.V[2]    // 0ae9eb76

	// Duplicate general-purpose register to vector
	VMOVQ		R4, V2.B16      // 82009f72
	VMOVQ		R5, V3.H8       // a3049f72
	VMOVQ		R6, V4.W4       // c4089f72
	VMOVQ		R7, V5.V2       // e50c9f72
	XVMOVQ		R16, X31.B32    // 1f029f76
	XVMOVQ		R17, X28.H16    // 3c069f76
	XVMOVQ		R18, X10.W8     // 4a0a9f76
	XVMOVQ		R19, X9.V4      // 690e9f76