CSW	X11, -1(X10)				// ERROR "must be in range [0, 127]"
	CSW	X11, 22(X10)				// ERROR "must be a multiple of 4"
	CSW	X11, 128(X10)				// ERROR "must be in range [0, 127]"
	CSD	F11, 24(X10)				// ERROR "expected integer prime register in rs2 position"
	CSD	X11, -1(X10)				// ERROR "must be in range [0, 255]"
	CSD	X11, 28(X10)				// ERROR "must be a multiple of 8"

	VLSEG4E64V	(X10), V0, V8			// 07740560

	VLSEG5E8V	(X10), V8			// 07040582
	VLSEG5E16V	(X10), V8			// 07540582
	VLSEG5E32V	(X10), V8			// 07640582
	VLSEG5E64V	(X10), V8			// 07740582
	VLSEG5E8V	(X10), V0, V8			// 07040580
	VLSEG5E16V	(X10), V0, V8			// 07540580
	VLSEG5E32V	(X10), V0, V8			// 07640580
	VLSEG5E64V	(X10), V0, V8			// 07740580

	VLSEG6E8V	(X10), V8			// 070405a2

	//
	VSETIVLI	X10, E32, M2, TA, MA, X12	// ERROR "expected immediate value"
	VLE8V		(X10), V1, V3			// ERROR "invalid vector mask register"
	VLE8FFV		(X10), V1, V3			// ERROR "invalid vector mask register"
	VSE8V		V3, V1, (X10)			// ERROR "invalid vector mask register"
	VLSE8V		(X10), X10, V1, V3		// ERROR "invalid vector mask register"
	VSSE8V		V3, X11, V1, (X10)		// ERROR "invalid vector mask register"

	VADDPD (AX), X29, X28       // 626195005820
	VADDPD (AX), X29, X10       // 627195005810
	VADDPD (AX), X10, X28       // 6261ad085820
	VADDPD (CX)(AX*1), X29, X0  // 62f19500580401
	VADDPD (CX)(AX*1), X1, X28  // 6261f508582401
	VADDPD (CX)(AX*1), X29, X28 // 62619500582401
	VADDPD (CX)(AX*1), X29, X10 // 62719500581401
	VADDPD (CX)(AX*1), X10, X28 // 6261ad08582401
	VADDPD (CX)(AX*2), X29, X0  // 62f19500580441

X10, X11, X12, X13, X14) SHA256ROUND0(4, X14, X15, X16, X17, X10, X11, X12, X13) SHA256ROUND0(5, X13, X14, X15, X16, X17, X10, X11, X12) SHA256ROUND0(6, X12, X13, X14, X15, X16, X17, X10, X11) SHA256ROUND0(7, X11, X12, X13, X14, X15, X16, X17, X10) SHA256ROUND0(8, X10, X11, X12, X13, X14, X15, X16, X17) SHA256ROUND0(9, X17, X10, X11, X12, X13, X14, X15, X16) SHA256ROUND0(10, X16, X17, X10, X11, X12, X13, X14, X15) SHA256ROUND0(11, X15, X16, X17, X10, X11, X12, X13, X14) SHA256ROUND0(12, X14, X15,...

X10, X11, X12, X13, X14) SHA256ROUND0(4, X14, X15, X16, X17, X10, X11, X12, X13) SHA256ROUND0(5, X13, X14, X15, X16, X17, X10, X11, X12) SHA256ROUND0(6, X12, X13, X14, X15, X16, X17, X10, X11) SHA256ROUND0(7, X11, X12, X13, X14, X15, X16, X17, X10) SHA256ROUND0(8, X10, X11, X12, X13, X14, X15, X16, X17) SHA256ROUND0(9, X17, X10, X11, X12, X13, X14, X15, X16) SHA256ROUND0(10, X16, X17, X10, X11, X12, X13, X14, X15) SHA256ROUND0(11, X15, X16, X17, X10, X11, X12, X13, X14) SHA256ROUND0(12, X14, X15,...

	{"R12", "R12"},
	{"R13", "R13"},
	{"R14", "R14"},
	{"R15", "R15"},
	{"R8", "R8"},
	{"R9", "R9"},
	{"g", "R14"},
	{"SI", "SI"},
	{"SP", "SP"},
	{"X0", "X0"},
	{"X1", "X1"},
	{"X10", "X10"},
	{"X11", "X11"},
	{"X12", "X12"},
	{"X13", "X13"},
	{"X14", "X14"},
	{"X15", "X15"},
	{"X2", "X2"},
	{"X3", "X3"},
	{"X4", "X4"},
	{"X5", "X5"},
	{"X6", "X6"},
	{"X7", "X7"},

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,
    X24,
    X25,
    X26,
    X27,

  private enum SmallEnum {
    X0,
    X1,
    X2
  }

  private enum MediumEnum {
    X0,
    X1,
    X2,
    X3,
    X4,
    X5,
    X6,
    X7,
    X8,
    X9,
    X10,
    X11,
    X12,
    X13,
    X14,
    X15,
    X16,
    X17,
    X18,
    X19,
    X20,
    X21,
    X22,
    X23,
    X24,
    X25,
    X26,
    X27,

	V4FMADDSS (DI), [X0-X3], K5, X22                   // 62e27f0d9b37 or 62e27f2d9b37 or 62e27f4d9b37
	V4FMADDSS 7(AX), [X10-X13], K5, X22                // 62e22f0d9bb007000000 or 62e22f2d9bb007000000 or 62e22f4d9bb007000000
	V4FMADDSS (DI), [X10-X13], K5, X22                 // 62e22f0d9b37 or 62e22f2d9b37 or 62e22f4d9b37