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Results 1 - 10 of 13 for SRAW (0.06 sec)

  1. src/cmd/internal/obj/riscv/anames.go

    	"LWU",
    	"LH",
    	"LHU",
    	"LB",
    	"LBU",
    	"SW",
    	"SH",
    	"SB",
    	"FENCE",
    	"FENCETSO",
    	"PAUSE",
    	"ADDIW",
    	"SLLIW",
    	"SRLIW",
    	"SRAIW",
    	"ADDW",
    	"SLLW",
    	"SRLW",
    	"SUBW",
    	"SRAW",
    	"LD",
    	"SD",
    	"MUL",
    	"MULH",
    	"MULHU",
    	"MULHSU",
    	"MULW",
    	"DIV",
    	"DIVU",
    	"REM",
    	"REMU",
    	"DIVW",
    	"DIVUW",
    	"REMW",
    	"REMUW",
    	"LRD",
    	"SCD",
    	"LRW",
    	"SCW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (Rsh32x8  <t> x y) && !shiftIsBounded(v) => (SRAW <t> x                 (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt8to64  y)))))
    (Rsh32x16 <t> x y) && !shiftIsBounded(v) => (SRAW <t> x                 (OR <y.Type> y (ADDI <y.Type> [-1] (SLTIU <y.Type> [32] (ZeroExt16to64 y)))))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
  3. test/codegen/shift.go

    	return v >> (s & 31)
    }
    
    func rshMask32x64(v int32, s uint64) int32 {
    	// arm64:"ASR",-"AND"
    	// ppc64x:"ISEL",-"ORN"
    	// riscv64:"SRAW","OR","SLTIU"
    	// s390x:-"RISBGZ",-"AND",-"LOCGR"
    	return v >> (s & 63)
    }
    
    func rsh5Mask32x64(v int32, s uint64) int32 {
    	// riscv64:"SRAW",-"OR",-"SLTIU"
    	return v >> (s & 31)
    }
    
    func lshMask64x32(v int64, s uint32) int64 {
    	// arm64:"LSL",-"AND"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/riscv64.s

    	SRLW	X5, X6, X7				// bb535300
    	SUBW	X5, X6, X7				// bb035340
    	SRAW	X5, X6, X7				// bb535340
    	ADDIW	$1, X6					// 1b031300
    	SLLIW	$1, X6					// 1b131300
    	SRLIW	$1, X6					// 1b531300
    	SRAIW	$1, X6					// 1b531340
    	ADDW	X5, X7					// bb835300
    	SLLW	X5, X7					// bb935300
    	SRLW	X5, X7					// bbd35300
    	SUBW	X5, X7					// bb835340
    	SRAW	X5, X7					// bbd35340
    	ADDW	$1, X6					// 1b031300
    	SLLW	$1, X6					// 1b131300
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/ppc64/anames.go

    	"NORCC",
    	"OR",
    	"ORCC",
    	"ORN",
    	"ORNCC",
    	"ORIS",
    	"REM",
    	"REMU",
    	"RFI",
    	"RLWMI",
    	"RLWMICC",
    	"RLWNM",
    	"RLWNMCC",
    	"CLRLSLWI",
    	"SLW",
    	"SLWCC",
    	"SRW",
    	"SRAW",
    	"SRAWCC",
    	"SRWCC",
    	"STBCCC",
    	"STHCCC",
    	"STSW",
    	"STWCCC",
    	"SUB",
    	"SUBCC",
    	"SUBVCC",
    	"SUBC",
    	"SUBCCC",
    	"SUBCV",
    	"SUBCVCC",
    	"SUBME",
    	"SUBMECC",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "SRA", argLength: 2, reg: gp21, asm: "SRA"},                   // arg0 >> (aux1 & 63), arithmetic right shift
    		{name: "SRAW", argLength: 2, reg: gp21, asm: "SRAW"},                 // arg0 >> (aux1 & 31), arithmetic right shift of 32 bit value, sign extended to 64 bits
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/PPC64Ops.go

    		{name: "SRAD", argLength: 2, reg: gp21cxer, asm: "SRAD"}, // signed arg0 >> (arg1&127), 64 bit width (note: 127, not 63!)
    		{name: "SRAW", argLength: 2, reg: gp21cxer, asm: "SRAW"}, // signed arg0 >> (arg1&63), 32 bit width
    		{name: "SRD", argLength: 2, reg: gp21, asm: "SRD"},       // unsigned arg0 >> (arg1&127), 64 bit width
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 22 19:59:38 UTC 2024
    - 43.8K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/PPC64.rules

    (Rsh32x(64|32)     <t> x y)  => (ISEL [0] (SRAW    <t> x y) (SRAWconst <t> x [31]) (CMP(U|WU)const y [32]))
    (Rsh32x16          <t> x y)  => (ISEL [2] (SRAW    <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0xFFE0] y)))
    (Rsh32x8           <t> x y)  => (ISEL [2] (SRAW    <t> x y) (SRAWconst <t> x [31]) (CMPconst [0] (ANDconst [0x00E0] y)))
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Jun 07 19:02:52 UTC 2024
    - 53.2K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/ppc64.s

    	SLDCC R3, R4                    // 7c841837
    
    	SRW $8, R3, R4                  // 5464c23e
    	SRW R3, R4, R5                  // 7c851c30
    	SRWCC R3, R4                    // 7c841c31
    	SRAW $8, R3, R4                 // 7c644670
    	SRAW R3, R4, R5                 // 7c851e30
    	SRAWCC R3, R4                   // 7c841e31
    	SRD $16, R3, R4                 // 78648402
    	SRD R3, R4, R5                  // 7c851c36
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/rewriteRISCV64.go

    		v.AuxInt = int64ToAuxInt(int64(y) >> uint32(x))
    		return true
    	}
    	return false
    }
    func rewriteValueRISCV64_OpRISCV64SRAW(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (SRAW x (MOVDconst [val]))
    	// result: (SRAIW [int64(val&31)] x)
    	for {
    		x := v_0
    		if v_1.Op != OpRISCV64MOVDconst {
    			break
    		}
    		val := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpRISCV64SRAIW)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 205.1K bytes
    - Viewed (0)
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