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Results 1 - 9 of 9 for UBFIZ (0.36 sec)
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test/codegen/bitfield.go
} // ubfiz // merge shifts into ubfiz: (x<<lc)>>rc && lc>rc func ubfiz1(x uint64) uint64 { // arm64:"UBFIZ\t[$]1, R[0-9]+, [$]60",-"LSL",-"LSR" // s390x:"RISBGZ\t[$]3, [$]62, [$]1, ",-"SLD",-"SRD" return (x << 4) >> 3 } // merge shift and zero-extension into ubfiz. func ubfiz2(x uint32) uint64 { return uint64(x+1) << 3 // arm64:"UBFIZ\t[$]3, R[0-9]+, [$]32",-"LSL" }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 23 06:11:32 UTC 2022 - 9.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
FNMSUBS F7, F25, F7, F22 <=> fnmsub s22, s7, s7, s25 (4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd> Examples: BFIW $16, R20, $6, R0 <=> bfi w0, w20, #16, #6 UBFIZ $34, R26, $5, R20 <=> ubfiz x20, x26, #34, #5 (5) FCCMPD, FCCMPS, FCCMPED, FCCMPES <cond>, Fm. Fn, $<nzcv> Examples:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 18 01:40:37 UTC 2023 - 5.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
// ubfiz // (x << lc) >> rc (SRLconst [rc] (SLLconst [lc] x)) && lc > rc => (UBFIZ [armBFAuxInt(lc-rc, 64-lc)] x) // uint64(x) << lc (SLLconst [lc] (MOVWUreg x)) => (UBFIZ [armBFAuxInt(lc, min(32, 64-lc))] x) (SLLconst [lc] (MOVHUreg x)) => (UBFIZ [armBFAuxInt(lc, min(16, 64-lc))] x) (SLLconst [lc] (MOVBUreg x)) => (UBFIZ [armBFAuxInt(lc, min(8, 64-lc))] x) // uint64(x << lc)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
// match: (SLLconst [sc] (UBFIZ [bfc] x)) // cond: sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64 // result: (UBFIZ [armBFAuxInt(bfc.getARM64BFlsb()+sc, bfc.getARM64BFwidth())] x) for { sc := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64UBFIZ { break } bfc := auxIntToArm64BitField(v_0.AuxInt) x := v_0.Args[0] if !(sc+bfc.getARM64BFwidth()+bfc.getARM64BFlsb() < 64) { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
// insert low width bits of arg0 into the result starting at bit lsb, bits to the left and right of the inserted bit field are zeroed {name: "UBFIZ", argLength: 1, reg: gp11, asm: "UBFIZ", aux: "ARM64BitField"}, // extract width bits of arg0 starting at bit lsb and insert at low end of result, remaining high bits are zeroed
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
ANDSW R10@>21, R2, ZR // 5f54ca6a ANDS R17<<11, R24, ZR // 1f2f11ea UBFIZW $3, R19, $14, R14 // 6e361d53 UBFIZ $3, R22, $14, R4 // c4367dd3 UBFXW $3, R7, $20, R15 // ef580353 UBFX $33, R17, $25, R5 // 25e661d3 UDIVW R8, R21, R15 // af0ac81a
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
STPW (R3, R4), x+8(SB) // bit field operation BFI $0, R1, $1, R2 // 220040b3 BFIW $0, R1, $1, R2 // 22000033 SBFIZ $0, R1, $1, R2 // 22004093 SBFIZW $0, R1, $1, R2 // 22000013 UBFIZ $0, R1, $1, R2 // 220040d3 UBFIZW $0, R1, $1, R2 // 22000053 // FSTPD/FSTPS/FLDPD/FLDPS FLDPD (R0), (F1, F2) // 0108406d FLDPD 8(R0), (F1, F2) // 0188406d
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 08 03:28:17 UTC 2023 - 94.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UBFIZ", auxType: auxARM64BitField, argLen: 1, asm: arm64.AUBFIZ, reg: regInfo{ inputs: []inputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)