Search Options

Results per page
Sort
Preferred Languages
Advance

Results 1 - 7 of 7 for x8 (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/avx512enc/avx512dq.s

    	VANDPD X11, X7, K7, X8                             // 6251c50f54c3
    	VANDPD -17(BP)(SI*2), X7, K7, X8                   // 6271c50f548475efffffff
    	VANDPD 7(AX)(CX*2), X7, K7, X8                     // 6271c50f54844807000000
    	VANDPD X22, X0, K7, X8                             // 6231fd0f54c6
    	VANDPD X1, X0, K7, X8                              // 6271fd0f54c1
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 194.8K bytes
    - Viewed (0)
  2. src/crypto/internal/nistec/fiat/p521_fiat64.go

    	var x878 uint64
    	x878, x877 = bits.Mul64(x8, arg2[8])
    	var x879 uint64
    	var x880 uint64
    	x880, x879 = bits.Mul64(x8, arg2[7])
    	var x881 uint64
    	var x882 uint64
    	x882, x881 = bits.Mul64(x8, arg2[6])
    	var x883 uint64
    	var x884 uint64
    	x884, x883 = bits.Mul64(x8, arg2[5])
    	var x885 uint64
    	var x886 uint64
    	x886, x885 = bits.Mul64(x8, arg2[4])
    	var x887 uint64
    	var x888 uint64
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 05 21:53:03 UTC 2022
    - 167K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/avx512enc/avx512bw.s

    	VPCMPGTB X26, X8, K1, K1                           // 62913d0964ca or 6291bd0964ca
    	VPCMPGTB (BX), X8, K1, K1                          // 62f13d09640b or 62f1bd09640b
    	VPCMPGTB -17(BP)(SI*1), X8, K1, K1                 // 62f13d09648c35efffffff or 62f1bd09648c35efffffff
    	VPCMPGTB X26, X8, K1, K3                           // 62913d0964da or 6291bd0964da
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 22 14:57:15 UTC 2018
    - 159.2K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/_gen/AMD64Ops.go

    	"SP",
    	"BP",
    	"SI",
    	"DI",
    	"R8",
    	"R9",
    	"R10",
    	"R11",
    	"R12",
    	"R13",
    	"g", // a.k.a. R14
    	"R15",
    	"X0",
    	"X1",
    	"X2",
    	"X3",
    	"X4",
    	"X5",
    	"X6",
    	"X7",
    	"X8",
    	"X9",
    	"X10",
    	"X11",
    	"X12",
    	"X13",
    	"X14",
    	"X15", // constant 0 in ABIInternal
    
    	// If you add registers, update asyncPreempt in runtime
    
    	// pseudo-registers
    	"SB",
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Aug 04 16:40:24 UTC 2023
    - 98K bytes
    - Viewed (1)
  5. src/vendor/golang.org/x/crypto/chacha20poly1305/chacha20poly1305_amd64.s

    #define shiftC1Left BYTE $0x66; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xff; BYTE $0x08 // PALIGNR $8, X7, X7
    #define shiftC2Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xc0; BYTE $0x08 // PALIGNR $8, X8, X8
    #define shiftC3Left BYTE $0x66; BYTE $0x45; BYTE $0x0f; BYTE $0x3a; BYTE $0x0f; BYTE $0xf6; BYTE $0x08 // PALIGNR $8, X14, X14
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Nov 29 21:28:33 UTC 2023
    - 105.6K bytes
    - Viewed (0)
  6. tensorflow/compiler/mlir/tensorflow/transforms/shape_inference.cc

      // Build the shape of the refined type, if lhs is unranked it
      // will be directly the shape of the refined type, otherwise we merged by
      // taking the most specialized. This combines `10x?x?` and `?x?x8` into
      // `10x?x8`.
      if (!lhs_shape_type.hasRank()) {
        if (rhs_shape_type.hasRank()) {
          shape.append(rhs_shape_type.getShape().begin(),
                       rhs_shape_type.getShape().end());
          refined_shape = true;
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Sat Jun 08 07:28:49 UTC 2024
    - 134.1K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    // left shift
    (Lsh(64|32|16|8)x64 <t> x y) && shiftIsBounded(v) => (SLL <t> x y)
    (Lsh(64|32|16|8)x32 <t> x y) && shiftIsBounded(v) => (SLL <t> x y)
    (Lsh(64|32|16|8)x16 <t> x y) && shiftIsBounded(v) => (SLL <t> x y)
    (Lsh(64|32|16|8)x8  <t> x y) && shiftIsBounded(v) => (SLL <t> x y)
    
    // signed right shift
    (Rsh64x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> x y)
    (Rsh32x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> (SignExt32to64 x) y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
Back to top