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Results 1 - 10 of 18 for R13 (0.06 seconds)
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src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, 0, &$4); // } SUB R14, R13 // 01ae6822 SUBU R14, R13 // 01ae6823 SUBV R4, R3 // 0064182e SUBVU R4, R3 // 0064182f // LSUBW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } SUB $6512, R13 // 21ade690 SUB $-6512, R13 // 21ad1970 SUBU $6512, R13 // 25ade690 SUBV $9531, R16 // 6210dac5 SUBV $-9531, R13 // 61ad253b SUBVU $9531, R16 // 6610dac5Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/amd64.s
JMP bar<>+4(SB)(R11*4) JCS 2(PC) JMP *4(SP) // JMP 4(SP) JCS 2(PC) JMP *(R12) // JMP (R12) JCS 2(PC) // JMP *(R12*4) // TODO: This line is silently dropped on the floor! JCS 2(PC) JMP *(R12)(R13*4) // JMP (R12)(R13*4) JCS 2(PC) JMP *(AX) // JMP (AX) JCS 2(PC) JMP *(SP) // JMP (SP) JCS 2(PC) // JMP *(AX*4) // TODO: This line is silently dropped on the floor! JCS 2(PC) JMP *(AX)(AX*4) // JMP (AX)(AX*4)
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Apr 09 18:57:21 GMT 2019 - 3.3K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
AMANDV R14, (R13), R12 // acb96238 AMORW R14, (R13), R12 // ac396338 AMORV R14, (R13), R12 // acb96338 AMXORW R14, (R13), R12 // ac396438 AMXORV R14, (R13), R12 // acb96438 AMMAXW R14, (R13), R12 // ac396538 AMMAXV R14, (R13), R12 // acb96538 AMMINW R14, (R13), R12 // ac396638 AMMINV R14, (R13), R12 // acb96638 AMMAXWU R14, (R13), R12 // ac396738 AMMAXVU R14, (R13), R12 // acb96738
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Nov 27 00:46:52 GMT 2025 - 44.5K bytes - Click Count (0) -
src/cmd/asm/internal/asm/operand_test.go
{"-12(R4)", "-12(R4)"}, {"0(PC)", "0(PC)"}, {"1024", "1024"}, {"12(R(1))", "12(R1)"}, {"12(R13)", "12(R13)"}, {"R0", "R0"}, {"R0->(32-1)", "R0->31"}, {"R0<<R1", "R0<<R1"}, {"R0>>R(1)", "R0>>R1"}, {"R0@>(32-1)", "R0@>31"}, {"R1", "R1"}, {"R11", "R11"}, {"R12", "R12"}, {"R13", "R13"}, {"R14", "R14"}, {"R15", "R15"}, {"R1<<2(R3)", "R1<<2(R3)"}, {"R(1)<<2(R(3))", "R1<<2(R3)"},Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Aug 29 18:31:05 GMT 2023 - 23.9K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
//TODO LDTR -0x1e(R3), R4 // 64285eb8 //TODO LDTR -0xe5(R3), R10 // 6ab851f8 //TODO LDTRB 0xf0(R13), R10 // aa094f38 //TODO LDTRH 0xe8(R13), R23 // b7894e78 //TODO LDTRSB -0x24(R20), R5 // 85cadd38 //TODO LDTRSB -0x75(R9), R13 // 2db99838 //TODO LDTRSH 0xef(R3), LR // 7ef8ce78 //TODO LDTRSH 0x96(R19), R24 // 786a8978
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Mon Jul 24 01:11:41 GMT 2023 - 43.9K bytes - Click Count (0) -
lib/fips140/v1.0.0-c2097c7c.zip
CMOVQEQ SI, R13 ANDQ R14, AX SHRQ $0x01, R11, R10 SHRQ $0x01, R12, R11 SHRQ $0x01, R13, R12 SHRQ $0x01, AX, R13 MOVQ R10, 32(SP) MOVQ R11, 40(SP) MOVQ R12, 48(SP) MOVQ R13, 56(SP) // ////////// MOVQ (SP), R10 MOVQ 8(SP), R11 MOVQ 16(SP), R12 MOVQ 24(SP), R13 MOVQ 96(SP), R14 MOVQ 104(SP), R15 MOVQ 112(SP), DI MOVQ 120(SP), SI CALL p256MulInternal(SB) MOVQ R10, 96(SP) MOVQ R11, 104(SP) MOVQ R12, 112(SP) MOVQ R13, 120(SP) XORQ AX, AX ADDQ R10, R10 ADCQ R11, R11 ADCQ R12, R12 ADCQ R13, R13 ADCQ $+0, AX MOVQ...
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Sep 25 19:53:19 GMT 2025 - 642.7K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VPGATHERQQ Y2, (BP)(Y7*2), Y1 // c4e2ed914c7d00 VPGATHERQQ X12, (R13)(X14*2), X11 // c40299915c7500 VPGATHERQQ Y12, (R13)(Y14*2), Y11 // c4029d915c7500 VPGATHERQQ X2, (BP)(X7*2), X1 // c4e2e9914c7d00 VPGATHERQQ Y2, (BP)(Y7*2), Y1 // c4e2ed914c7d00 VPGATHERQQ X12, (R13)(X14*2), X11 // c40299915c7500 VPGATHERQQ Y12, (R13)(Y14*2), Y11 // c4029d915c7500
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Feb 20 11:20:03 GMT 2025 - 57.7K bytes - Click Count (0) -
lib/fips140/v1.1.0-rc1.zip
CMOVQEQ SI, R13 ANDQ R14, AX SHRQ $0x01, R11, R10 SHRQ $0x01, R12, R11 SHRQ $0x01, R13, R12 SHRQ $0x01, AX, R13 MOVQ R10, 32(SP) MOVQ R11, 40(SP) MOVQ R12, 48(SP) MOVQ R13, 56(SP) // ////////// MOVQ (SP), R10 MOVQ 8(SP), R11 MOVQ 16(SP), R12 MOVQ 24(SP), R13 MOVQ 96(SP), R14 MOVQ 104(SP), R15 MOVQ 112(SP), DI MOVQ 120(SP), SI CALL p256MulInternal(SB) MOVQ R10, 96(SP) MOVQ R11, 104(SP) MOVQ R12, 112(SP) MOVQ R13, 120(SP) XORQ AX, AX ADDQ R10, R10 ADCQ R11, R11 ADCQ R12, R12 ADCQ R13, R13 ADCQ $+0, AX MOVQ...
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Thu Dec 11 16:27:41 GMT 2025 - 663K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
CSINV HS, R1, R2, R3 // 232082da CSINVW MI, R2, ZR, R2 // 42409f5a CINC EQ, R4, R9 // 8914849a CINCW PL, R2, ZR // 5f44821a CINV PL, R11, R22 // 76418bda CINVW LS, R7, R13 // ed80875a CNEG LS, R13, R7 // a7858dda CNEGW EQ, R8, R13 // 0d15885a // atomic ops LDARB (R25), R2 // 22ffdf08 LDARH (R5), R7 // a7fcdf48
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Mon Nov 10 17:34:13 GMT 2025 - 96.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/arm64error.s
VLD1 (R8)(R13), [V2.B16] // ERROR "illegal combination" VLD1 8(R9), [V2.B16] // ERROR "illegal combination" VST1 [V1.B16], (R8)(R13) // ERROR "illegal combination" VST1 [V1.B16], 9(R2) // ERROR "illegal combination"
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Oct 14 19:00:00 GMT 2025 - 38.4K bytes - Click Count (0)