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Results 1 - 7 of 7 for R13 (0.11 sec)

  1. src/cmd/asm/internal/asm/testdata/mips64.s

    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SUB	R14, R13	// 01ae6822
    	SUBU	R14, R13	// 01ae6823
    	SUBV	R4, R3		// 0064182e
    	SUBVU	R4, R3		// 0064182f
    //	LSUBW imm ',' rreg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	SUB	$6512, R13	// 21ade690
    	SUB	$-6512, R13	// 21ad1970
    	SUBU	$6512, R13	// 25ade690
    	SUBV	$9531, R16	// 6210dac5
    	SUBV	$-9531, R13	// 61ad253b
    	SUBVU	$9531, R16	// 6610dac5
    
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
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  2. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	//TODO LDTR -0x1e(R3), R4                  // 64285eb8
    	//TODO LDTR -0xe5(R3), R10                 // 6ab851f8
    	//TODO LDTRB 0xf0(R13), R10                // aa094f38
    	//TODO LDTRH 0xe8(R13), R23                // b7894e78
    	//TODO LDTRSB -0x24(R20), R5               // 85cadd38
    	//TODO LDTRSB -0x75(R9), R13               // 2db99838
    	//TODO LDTRSH 0xef(R3), LR                 // 7ef8ce78
    	//TODO LDTRSH 0x96(R19), R24               // 786a8978
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Mon Jul 24 01:11:41 GMT 2023
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  3. src/cmd/asm/internal/asm/operand_test.go

    	{"-12(R4)", "-12(R4)"},
    	{"0(PC)", "0(PC)"},
    	{"1024", "1024"},
    	{"12(R(1))", "12(R1)"},
    	{"12(R13)", "12(R13)"},
    	{"R0", "R0"},
    	{"R0->(32-1)", "R0->31"},
    	{"R0<<R1", "R0<<R1"},
    	{"R0>>R(1)", "R0>>R1"},
    	{"R0@>(32-1)", "R0@>31"},
    	{"R1", "R1"},
    	{"R11", "R11"},
    	{"R12", "R12"},
    	{"R13", "R13"},
    	{"R14", "R14"},
    	{"R15", "R15"},
    	{"R1<<2(R3)", "R1<<2(R3)"},
    	{"R(1)<<2(R(3))", "R1<<2(R3)"},
    Go
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 29 18:31:05 GMT 2023
    - 23.9K bytes
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  4. src/cmd/asm/internal/asm/testdata/arm64.s

    	CSINV	HS, R1, R2, R3	// 232082da
    	CSINVW	MI, R2, ZR, R2	// 42409f5a
    	CINC	EQ, R4, R9	// 8914849a
    	CINCW	PL, R2, ZR	// 5f44821a
    	CINV	PL, R11, R22	// 76418bda
    	CINVW	LS, R7, R13	// ed80875a
    	CNEG	LS, R13, R7	// a7858dda
    	CNEGW	EQ, R8, R13	// 0d15885a
    
    // atomic ops
    	LDARB	(R25), R2                            // 22ffdf08
    	LDARH	(R5), R7                             // a7fcdf48
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
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  5. src/cmd/asm/internal/asm/testdata/arm64error.s

    	VLD1	(R8)(R13), [V2.B16]                              // ERROR "illegal combination"
    	VLD1	8(R9), [V2.B16]                                  // ERROR "illegal combination"
    	VST1	[V1.B16], (R8)(R13)                              // ERROR "illegal combination"
    	VST1	[V1.B16], 9(R2)                                  // ERROR "illegal combination"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
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  6. doc/asm.html

    The assembler uses them to hold temporary values when assembling some instructions.
    </p>
    
    <p>
    <code>R13</code> points to the <code>g</code> (goroutine) structure.
    This register must be referred to as <code>g</code>; the name <code>R13</code> is not recognized.
    </p>
    
    <p>
    <code>R15</code> points to the stack frame and should typically only be accessed using the
    HTML
    - Registered: Tue May 07 11:14:38 GMT 2024
    - Last Modified: Tue Nov 28 19:15:27 GMT 2023
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  7. src/cmd/asm/internal/asm/testdata/amd64error.s

    	EXTRACTPS $4, X2, (BX)          // ERROR "invalid instruction"
    	EXTRACTPS $-1, X2, (BX)         // ERROR "invalid instruction"
    	// VSIB addressing does not permit non-vector (X/Y)
    	// scaled index register.
    	VPGATHERDQ X12,(R13)(AX*2), X11 // ERROR "invalid instruction"
    	VPGATHERDQ X2, 664(BX*1), X1    // ERROR "invalid instruction"
    	VPGATHERDQ Y2, (BP)(AX*2), Y1   // ERROR "invalid instruction"
    	VPGATHERDQ Y5, 664(DX*8), Y6    // ERROR "invalid instruction"
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    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Jun 14 00:03:57 GMT 2023
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