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src/cmd/asm/internal/asm/testdata/amd64error.s
Others - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Viewed (0) -
doc/asm.html
Instead, the compiler operates on a kind of semi-abstract instruction set, and instruction selection occurs partly after code generation. The assembler works on the semi-abstract form, so when you see an instruction like <code>MOV</code> what the toolchain actually generates for that operation might not be a move instruction at all, perhaps a clear or load. Or it might correspond exactly to the machine instruction with that name.
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src/cmd/asm/internal/arch/arch.go
instructions["JZ"] = x86.AJEQ /* alternate */ instructions["MASKMOVDQU"] = x86.AMASKMOVOU instructions["MOVD"] = x86.AMOVQ instructions["MOVDQ2Q"] = x86.AMOVQ instructions["MOVNTDQ"] = x86.AMOVNTO instructions["MOVOA"] = x86.AMOVO instructions["PSLLDQ"] = x86.APSLLO instructions["PSRLDQ"] = x86.APSRLO instructions["PADDD"] = x86.APADDL // Spellings originally used in CL 97235.
Go - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Tue Mar 21 06:51:28 GMT 2023 - 21.3K bytes - Viewed (0) -
.github/bot_config.yml
*TensorFlow release binaries version 1.6 and higher are prebuilt with AVX instruction sets.* Therefore on any CPU that does not have these instruction sets, either CPU or GPU version of TF will fail to load. Apparently, your CPU model does not support AVX instruction sets. You can still use TensorFlow with the alternatives given below: * Try Google Colab to use TensorFlow.
Others - Registered: Tue Apr 23 12:39:09 GMT 2024 - Last Modified: Tue Oct 17 11:48:07 GMT 2023 - 4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
} p.errorf("wrong number of arguments to %s instruction", op) return case 4: if p.arch.Family == sys.S390X || p.arch.Family == sys.PPC64 { // 4-operand compare-and-branch. prog.From = a[0] prog.Reg = p.getRegister(prog, op, &a[1]) prog.AddRestSource(a[2]) target = &a[3] break } p.errorf("wrong number of arguments to %s instruction", op) return default:
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src/cmd/asm/internal/asm/testdata/riscv64error.s
MOVWU X5, (X6) // ERROR "unsupported unsigned store" MOVF F0, F1, F2 // ERROR "illegal MOV instruction" MOVD F0, F1, F2 // ERROR "illegal MOV instruction" MOV X10, X11, X12 // ERROR "illegal MOV instruction" MOVW X10, X11, X12 // ERROR "illegal MOV instruction" RORI $64, X5, X6 // ERROR "immediate out of range 0 to 63" SLLI $64, X5, X6 // ERROR "immediate out of range 0 to 63"
Others - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Sun Apr 07 03:32:27 GMT 2024 - 2.8K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
// BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg". func IsARMBFX(op obj.As) bool { switch op { case arm.ABFX, arm.ABFXU, arm.ABFC, arm.ABFI: return true } return false } // IsARMFloatCmp reports whether the op is a floating comparison instruction. func IsARMFloatCmp(op obj.As) bool { switch op {
Go - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Fri Nov 18 17:59:44 GMT 2022 - 6.1K bytes - Viewed (0) -
src/cmd/asm/internal/arch/riscv64.go
// This file encapsulates some of the odd characteristics of the RISCV64 // instruction set, to minimize its interaction with the core of the // assembler. package arch import ( "cmd/internal/obj" "cmd/internal/obj/riscv" ) // IsRISCV64AMO reports whether the op (as defined by a riscv.A* // constant) is one of the AMO instructions that requires special // handling. func IsRISCV64AMO(op obj.As) bool { switch op {
Go - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Sun Mar 15 08:13:28 GMT 2020 - 943 bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/386.s
// This input was created by taking the instruction productions in // the old assembler's (8a's) grammar and hand-writing complete // instructions for each rule, to guarantee we cover the same space. #include "../../../../../runtime/textflag.h" TEXT foo(SB), DUPOK|NOSPLIT, $0 // LTYPE1 nonrem { outcode(int($1), &$2); } SETCC AX SETCC foo+4(SB) // LTYPE2 rimnon { outcode(int($1), &$2); } DIVB AX DIVB foo+4(SB) PUSHL $foo+4(SB)
Others - Registered: Tue Apr 23 11:13:09 GMT 2024 - Last Modified: Tue Apr 09 18:57:21 GMT 2019 - 2K bytes - Viewed (0) -
src/cmd/asm/internal/asm/line_test.go
{"VADDPD.RZ_SAE.SAE X0, X1, X2", `bad suffix combination`}, // BSWAP on 16-bit registers is undefined. See #29167, {"BSWAPW DX", `unrecognized instruction`}, {"BSWAPW R11", `unrecognized instruction`}, }) } func testBadInstParser(t *testing.T, goarch string, tests []badInstTest) { for i, test := range tests { arch, ctxt := setArch(goarch)
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