// LTYPERT spec10	{ outcode($1, &$2); }
	JCS	2(PC)
	RETFL	$4

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

	// Intel pseudonyms for our own renamings.
	PADDD	M2, M1 // PADDL M2, M1
	MOVDQ2Q	X1, M1 // MOVQ X1, M1
	MOVNTDQ	X1, (AX)	// MOVNTO X1, (AX)
	MOVOA	(AX), X1	// MOVO (AX), X1

// Tests for SP indexed addresses.
	MOVQ	foo(SP)(AX*1), BX		// 488b1c04

	instructions["MOVDQ2Q"] = x86.AMOVQ
	instructions["MOVNTDQ"] = x86.AMOVNTO
	instructions["MOVOA"] = x86.AMOVO
	instructions["PSLLDQ"] = x86.APSLLO
	instructions["PSRLDQ"] = x86.APSRLO
	instructions["PADDD"] = x86.APADDL
	// Spellings originally used in CL 97235.
	instructions["MOVBELL"] = x86.AMOVBEL
	instructions["MOVBEQQ"] = x86.AMOVBEQ
	instructions["MOVBEWW"] = x86.AMOVBEW

	return &Arch{

PSHUFB X8, X0 VMOVDQA X0, X6 PADDD 96(AX), X0 SHA256RNDS2 X0, X1, X2 VMOVDQA X6, X7 PALIGNR $0x04, X5, X7 PADDD X7, X3 SHA256MSG2 X6, X3 PSHUFD $0x0e, X0, X0 SHA256RNDS2 X0, X2, X1 SHA256MSG1 X6, X5 VMOVDQA X3, X0 PADDD 128(AX), X0 SHA256RNDS2 X0, X1, X2 VMOVDQA X3, X7 PALIGNR $0x04, X6, X7 PADDD X7, X4 SHA256MSG2 X3, X4 PSHUFD $0x0e, X0, X0 SHA256RNDS2 X0, X2, X1 SHA256MSG1 X3, X6 VMOVDQA X4, X0 PADDD 160(AX), X0 SHA256RNDS2 X0, X1, X2 VMOVDQA X4, X7 PALIGNR $0x04, X3, X7 PADDD X7, X5 SHA256MSG2 X4, X5...