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Results 1 - 10 of 11 for R12 (0.57 sec)

  1. src/cmd/asm/internal/asm/testdata/amd64.s

    	JMP	foo+4(SB)
    	JCS	2(PC)
    	JMP	bar<>+4(SB)
    	JCS	2(PC)
    	JMP	bar<>+4(SB)(R11*4)
    	JCS	2(PC)
    	JMP	*4(SP) // JMP 4(SP)
    	JCS	2(PC)
    	JMP	*(R12) // JMP (R12)
    	JCS	2(PC)
    //	JMP	*(R12*4) // TODO: This line is silently dropped on the floor!
    	JCS	2(PC)
    	JMP	*(R12)(R13*4) // JMP (R12)(R13*4)
    	JCS	2(PC)
    	JMP	*(AX) // JMP (AX)
    	JCS	2(PC)
    	JMP	*(SP) // JMP (SP)
    	JCS	2(PC)
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Apr 09 18:57:21 GMT 2019
    - 3.3K bytes
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  2. src/cmd/asm/internal/lex/lex_test.go

    			"\tMOVBLZX	(off*4)(R12),	reg \\",
    			"\tADDB	reg,		DX",
    			"",
    			"LOAD(8, AX)",
    		),
    		"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n",
    	},
    	{
    		"nested multiline macro",
    		lines(
    			"#define KEYROUND(xmm, load, off, r1, r2, index) \\",
    			"\tMOVBLZX	(BP)(DX*4),	R8 \\",
    			"\tload((off+1), r2) \\",
    			"\tMOVB	R8,		(off*4)(R12) \\",
    			"\tPINSRW	$index, (BP)(R8*4), xmm",
    Go
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 29 07:48:38 GMT 2023
    - 5.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LMOVH rreg ',' addr
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVH	R13, (R7)	// a4ed0000
    	MOVH	R10, 61(R23)	// a6ea003d
    	MOVH	R8, -33(R12)	// a588ffdf
    	MOVHU	R13, (R7)	// a4ed0000
    	MOVHU	R10, 61(R23)	// a6ea003d
    	MOVHU	R8, -33(R12)	// a588ffdf
    
    //	LMOVB rreg ',' addr
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVB	R1, foo<>+3(SB)
    	MOVB	R5, -18(R4)	// a085ffee
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 12.4K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	LDAXRH (R5), R8                            // a8fc5f48
    	//TODO LDNP 0xcc(RSP), ZR, R12             // ecff5928
    	//TODO LDNP 0x40(R28), R9, R5              // 852744a8
    	//TODO LDPSW -0xd0(R2), R0, R12            // 4c00e668
    	//TODO LDPSW 0x5c(R4), R8, R5              // 85a0cb69
    	//TODO LDPSW 0x6c(R12), R2, R27            // 9b894d69
    	MOVWU.P -84(R15), R9                       // e9c55ab8
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Mon Jul 24 01:11:41 GMT 2023
    - 43.9K bytes
    - Viewed (1)
  5. src/cmd/asm/internal/asm/operand_test.go

    	{"AL", "AL"},
    	{"AX", "AX"},
    	{"BP", "BP"},
    	{"BX", "BX"},
    	{"CX", "CX"},
    	{"DI", "DI"},
    	{"DX", "DX"},
    	{"R10", "R10"},
    	{"R10", "R10"},
    	{"R11", "R11"},
    	{"R12", "R12"},
    	{"R13", "R13"},
    	{"R14", "R14"},
    	{"R15", "R15"},
    	{"R8", "R8"},
    	{"R9", "R9"},
    	{"g", "R14"},
    	{"SI", "SI"},
    	{"SP", "SP"},
    	{"X0", "X0"},
    	{"X1", "X1"},
    	{"X10", "X10"},
    Go
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 29 18:31:05 GMT 2023
    - 23.9K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/s390x.s

    	LAAG	R4, R5, -524288(R6)   // eb54600080e8
    	LAAL	R7, R8, 8192(R9)      // eb87900002fa
    	LAALG	R10, R11, -8192(R12)  // ebbac000feea
    	LAN	R1, R2, (R3)          // eb21300000f4
    	LANG	R4, R5, (R6)          // eb54600000e4
    	LAX	R7, R8, (R9)          // eb87900000f7
    	LAXG	R10, R11, (R12)       // ebbac00000e7
    	LAO	R1, R2, (R3)          // eb21300000f6
    	LAOG	R4, R5, (R6)          // eb54600000e6
    
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Nov 22 03:55:32 GMT 2023
    - 21.6K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/arm64.s

    	ADD	R2.SXTX<<1, RSP, RSP            // ffe7228b
    	ADD	ZR.SXTX<<1, R2, R3              // 43e43f8b
    	ADDW	R2.SXTW, R10, R12               // 4cc1220b
    	ADD	R19.UXTX, R14, R17              // d161338b
    	ADDSW	R19.UXTW, R14, R17              // d141332b
    	ADDS	R12.SXTX, R3, R1                // 61e02cab
    	SUB	R19.UXTH<<4, R2, R21            // 553033cb
    	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
    - 94.9K bytes
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  8. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	VPGATHERQQ X0, 16(SP)(X1*1), X2         // c4e2f991540c10
    	VPGATHERQQ X0, 512(SP)(X1*1), X2        // c4e2f991940c00020000
    	VPGATHERQQ X0, (R12)(X1*1), X2          // c4c2f991140c
    	VPGATHERQQ X0, 16(R12)(X1*1), X2        // c4c2f991540c10
    	VPGATHERQQ X0, 512(R12)(X1*1), X2       // c4c2f991940c00020000
    	VPGATHERQQ X0, (BP)(X1*1), X2           // c4e2f991540d00
    	VPGATHERQQ X0, 16(BP)(X1*1), X2         // c4e2f991540d10
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Apr 11 18:32:50 GMT 2023
    - 57.6K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/armv6.s

    	ABSD	F4, F5        // c45bb0ee
    	SQRTF	F0, F1        // c01ab1ee
    	SQRTD	F4, F5        // c45bb1ee
    	MOVFD	F0, F1        // c01ab7ee
    	MOVDF	F4, F5        // c45bb7ee
    
    	LDREX	(R8), R9      // 9f9f98e1
    	LDREXD	(R11), R12    // 9fcfbbe1
    	STREX	R3, (R4), R5  // STREX  (R4), R3, R5 // 935f84e1
    	STREXD	R8, (R9), g   // STREXD (R9), R8, g  // 98afa9e1
    
    	CMPF    F8, F9        // c89ab4ee10faf1ee
    	CMPD.CS F4, F5        // c45bb42e10faf12e
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Thu Dec 21 16:30:51 GMT 2017
    - 4.6K bytes
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  10. doc/asm.html

    <code>&gt;&gt;</code> (logical right shift), and
    <code>@&gt;</code> (rotate right).
    
    </li>
    
    <li>
    <code>[R0,g,R12-R15]</code>: For multi-register instructions, the set comprising
    <code>R0</code>, <code>g</code>, and <code>R12</code> through <code>R15</code> inclusive.
    </li>
    
    <li>
    <code>(R5, R6)</code>: Destination register pair.
    </li>
    
    </ul>
    
    HTML
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Nov 28 19:15:27 GMT 2023
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