"ADDW",
	"DIVW",
	"DIVWU",
	"DIVD",
	"DIVDU",
	"MODW",
	"MODWU",
	"MODD",
	"MODDU",
	"MULLW",
	"MULLD",
	"MULHD",
	"MULHDU",
	"MLGR",
	"SUB",
	"SUBC",
	"SUBV",
	"SUBE",
	"SUBW",
	"NEG",
	"NEGW",
	"MOVWBR",
	"MOVB",
	"MOVBZ",
	"MOVH",
	"MOVHBR",
	"MOVHZ",
	"MOVW",
	"MOVWZ",
	"MOVD",
	"MOVDBR",
	"MOVDEQ",
	"MOVDGE",
	"MOVDGT",
	"MOVDLE",
	"MOVDLT",

	STXRH R12, (R3), R8                        // 6c7c0848
	SUBW R20.UXTW<<2, R23, R19                 // f34a344b
	SUB R5.SXTW<<2, R1, R26                    // 3ac825cb
	SUB $(1923<<12), R4, R27                   // SUB $7876608, R4, R27         // 9b0c5ed1
	SUBW $(1923<<12), R4, R27                  // SUBW $7876608, R4, R27        // 9b0c5e51
	SUBW R12<<29, R7, R8                       // e8740c4b

(ADDW x (MOVDconst [c])) => (ADDWconst [int32(c)] x)

(SUB x (MOVDconst [c])) && is32Bit(c) => (SUBconst x [int32(c)])
(SUB (MOVDconst [c]) x) && is32Bit(c) => (NEG (SUBconst <v.Type> x [int32(c)]))
(SUBW x (MOVDconst [c])) => (SUBWconst x [int32(c)])
(SUBW (MOVDconst [c]) x) => (NEGW (SUBWconst <v.Type> x [int32(c)]))

(MULLD x (MOVDconst [c])) && is32Bit(c) => (MULLDconst [int32(c)] x)
(MULLW x (MOVDconst [c])) => (MULLWconst [int32(c)] x)

(SUB <t> (MOVDconst [val]) y) && is32Bit(-val) => (NEG (ADDI <t> [-val] y))

// Subtraction of zero.
(SUB  x (MOVDconst [0])) => x
(SUBW x (MOVDconst [0])) => (ADDIW [0] x)

// Subtraction from zero.
(SUB  (MOVDconst [0]) x) => (NEG x)
(SUBW (MOVDconst [0]) x) => (NEGW x)

// Fold negation into subtraction.
(NEG (SUB x y)) => (SUB y x)

		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB", clobberFlags: true},                                                                                       // arg0 - arg1
		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW", clobberFlags: true},                                                                                     // arg0 - arg1

		{name: "NEGW", argLength: 1, reg: gp11, asm: "NEGW"},                  // -arg0 of 32 bits, sign extended to 64 bits
		{name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},                    // arg0 - arg1
		{name: "SUBW", argLength: 2, reg: gp21, asm: "SUBW"},                  // 32 low bits of arg 0 - 32 low bits of arg 1, sign extended to 64 bits

		// M extension. H means high (i.e., it returns the top bits of

	"STI",
	"STMXCSR",
	"STOSB",
	"STOSL",
	"STOSQ",
	"STOSW",
	"STRL",
	"STRQ",
	"STRW",
	"SUBB",
	"SUBL",
	"SUBPD",
	"SUBPS",
	"SUBQ",
	"SUBSD",
	"SUBSS",
	"SUBW",
	"SWAPGS",
	"SYSCALL",
	"SYSENTER",
	"SYSENTER64",
	"SYSEXIT",
	"SYSEXIT64",
	"SYSRET",
	"TESTB",
	"TESTL",
	"TESTQ",
	"TESTW",
	"TPAUSE",
	"TZCNTL",
	"TZCNTQ",

	SUBW $7, (R11)                          // 6641832b07
	SUBW $7, DX                             // 6683ea07
	SUBW $7, R11                            // 664183eb07
	SUBW DX, (BX)                           // 662913
	SUBW R11, (BX)                          // 6644291b
	SUBW DX, (R11)                          // 66412913
	SUBW R11, (R11)                         // 6645291b

	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
	SUBS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"

	ADDSW	R19.UXTW, R14, R17              // d141332b
	ADDS	R12.SXTX, R3, R1                // 61e02cab
	SUB	R19.UXTH<<4, R2, R21            // 553033cb
	SUBW	R1.UXTX<<1, R3, R2              // 6264214b
	SUBS	R3.UXTX, R8, R9                 // 096123eb
	SUBSW	R17.UXTH, R15, R21              // f521316b
	SUBW	ZR<<14, R19, R13                // 6d3a1f4b
	CMP	R2.SXTH, R13                    // bfa122eb
	CMN	R1.SXTX<<2, R10                 // 5fe921ab