VDIVESD V1, V2, V3                      // 106113cb
	VDIVESQ V1, V2, V3                      // 1061130b
	VDIVESW V1, V2, V3                      // 1061138b
	VDIVEUD V1, V2, V3                      // 106112cb
	VDIVEUQ V1, V2, V3                      // 1061120b
	VDIVEUW V1, V2, V3                      // 1061128b
	VDIVSD V1, V2, V3                       // 106111cb
	VDIVSQ V1, V2, V3                       // 1061110b

	"VEXTDUBVLX",
	"VEXTDDVRX",
	"VEXTDDVLX",
	"VEXPANDWM",
	"VEXPANDQM",
	"VEXPANDHM",
	"VEXPANDDM",
	"VEXPANDBM",
	"VDIVUW",
	"VDIVUQ",
	"VDIVUD",
	"VDIVSW",
	"VDIVSQ",
	"VDIVSD",
	"VDIVEUW",
	"VDIVEUQ",
	"VDIVEUD",
	"VDIVESW",
	"VDIVESQ",
	"VDIVESD",
	"VCTZDM",
	"VCNTMBW",
	"VCNTMBH",
	"VCNTMBD",
	"VCNTMBB",
	"VCMPUQ",
	"VCMPSQ",
	"VCMPGTUQCC",

	VCTZDM:         "vctzdm",
	VDIVESD:        "vdivesd",
	VDIVESQ:        "vdivesq",
	VDIVESW:        "vdivesw",
	VDIVEUD:        "vdiveud",
	VDIVEUQ:        "vdiveuq",
	VDIVEUW:        "vdiveuw",
	VDIVSD:         "vdivsd",
	VDIVSQ:         "vdivsq",
	VDIVSW:         "vdivsw",
	VDIVUD:         "vdivud",
	VDIVUQ:         "vdivuq",
	VDIVUW:         "vdivuw",
	VEXPANDBM:      "vexpandbm",

	"SLLIW",
	"SRLIW",
	"SRAIW",
	"ADDW",
	"SLLW",
	"SRLW",
	"SUBW",
	"SRAW",
	"LD",
	"SD",
	"MUL",
	"MULH",
	"MULHU",
	"MULHSU",
	"MULW",
	"DIV",
	"DIVU",
	"REM",
	"REMU",
	"DIVW",
	"DIVUW",
	"REMW",
	"REMUW",
	"LRD",
	"SCD",
	"LRW",
	"SCW",
	"AMOSWAPD",
	"AMOADDD",
	"AMOANDD",
	"AMOORD",
	"AMOXORD",
	"AMOMAXD",
	"AMOMAXUD",
	"AMOMIND",

	VDIVPD Z16, Z21, K3, Z14                           // 6231d5435ef0
	VDIVPD Z9, Z21, K3, Z14                            // 6251d5435ef1
	VDIVPD Z16, Z8, K3, Z14                            // 6231bd4b5ef0
	VDIVPD Z9, Z8, K3, Z14                             // 6251bd4b5ef1
	VDIVPD Z16, Z21, K3, Z15                           // 6231d5435ef8
	VDIVPD Z9, Z21, K3, Z15                            // 6251d5435ef9

// one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
func IsMIPSMUL(op obj.As) bool {
	switch op {
	case mips.AMUL, mips.AMULU, mips.AMULV, mips.AMULVU,
		mips.ADIV, mips.ADIVU, mips.ADIVV, mips.ADIVVU,
		mips.AREM, mips.AREMU, mips.AREMV, mips.AREMVU,
		mips.AMADD, mips.AMSUB:
		return true
	}
	return false
}

func mipsRegisterNumber(name string, n int16) (int16, bool) {

// Copyright 2017 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

TEXT ·f(SB),0,$0-8
	MOVW	x+0(FP), R1
	MOVW	x+4(FP), R2
	DIVU	R1, R2
	DIV	R1, R2
	MODU	R1, R2
	MOD	R1, R2

// one of the MUL/DIV/REM instructions that require special handling.
func IsLoong64MUL(op obj.As) bool {
	switch op {
	case loong64.AMUL, loong64.AMULU, loong64.AMULV, loong64.AMULVU,
		loong64.ADIV, loong64.ADIVU, loong64.ADIVV, loong64.ADIVVU,
		loong64.AREM, loong64.AREMU, loong64.AREMV, loong64.AREMVU:
		return true
	}
	return false
}

// IsLoong64RDTIME reports whether the op (as defined by an loong64.A*

	"FNMULAD",
	"FMULSF",
	"FMULSD",
	"FNMULSF",
	"FNMULSD",
	"DIVF",
	"DIVD",
	"SQRTF",
	"SQRTD",
	"ABSF",
	"ABSD",
	"NEGF",
	"NEGD",
	"SRL",
	"SRA",
	"SLL",
	"MULU",
	"DIVU",
	"MUL",
	"MMUL",
	"DIV",
	"MOD",
	"MODU",
	"DIVHW",
	"DIVUHW",
	"MOVB",
	"MOVBS",
	"MOVBU",
	"MOVH",
	"MOVHS",
	"MOVHU",
	"MOVW",
	"MOVM",
	"SWPBU",
	"SWPW",
	"RFE",

(Div(64|32)F ...) => (FDIV(D|S) ...)

(Div64 x y [false])  => (DIV x y)
(Div64u ...) => (DIVU ...)
(Div32 x y [false])  => (DIVW x y)
(Div32u ...) => (DIVUW ...)
(Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
(Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y)   => (DIVW  (SignExt8to32 x)  (SignExt8to32 y))
(Div8u x y)  => (DIVUW (ZeroExt8to32 x)  (ZeroExt8to32 y))

(Hmul64 ...)  => (MULH  ...)