"VSLO",
	"VSRB",
	"VSRH",
	"VSRW",
	"VSR",
	"VSRO",
	"VSLD",
	"VSRD",
	"VSA",
	"VSRAB",
	"VSRAH",
	"VSRAW",
	"VSRAD",
	"VSOI",
	"VSLDOI",
	"VCLZ",
	"VCLZB",
	"VCLZH",
	"VCLZW",
	"VCLZD",
	"VPOPCNT",
	"VPOPCNTB",
	"VPOPCNTH",
	"VPOPCNTW",
	"VPOPCNTD",
	"VCMPEQ",
	"VCMPEQUB",
	"VCMPEQUBCC",
	"VCMPEQUH",
	"VCMPEQUHCC",
	"VCMPEQUW",

	VSRAW V1, V2, V3                // 10611384
	VSRAD V1, V2, V3                // 106113c4
	VSLDOI $3, V1, V2, V3           // 106110ec
	VCLZB V1, V2                    // 10400f02
	VCLZH V1, V2                    // 10400f42
	VCLZW V1, V2                    // 10400f82
	VCLZD V1, V2                    // 10400fc2
	VPOPCNTB V1, V2                 // 10400f03
	VPOPCNTH V1, V2                 // 10400f43

	VADDUDM:        "vaddudm",
	VADDUQM:        "vadduqm",
	VBPERMQ:        "vbpermq",
	VCIPHER:        "vcipher",
	VCIPHERLAST:    "vcipherlast",
	VCLZB:          "vclzb",
	VCLZD:          "vclzd",
	VCLZH:          "vclzh",
	VCLZW:          "vclzw",
	VCMPEQUD:       "vcmpequd",
	VCMPEQUDCC:     "vcmpequd.",
	VCMPGTSD:       "vcmpgtsd",
	VCMPGTSDCC:     "vcmpgtsd.",
	VCMPGTUD:       "vcmpgtud",

	"VCHG",
	"VCHBS",
	"VCHHS",
	"VCHFS",
	"VCHGS",
	"VCHL",
	"VCHLB",
	"VCHLH",
	"VCHLF",
	"VCHLG",
	"VCHLBS",
	"VCHLHS",
	"VCHLFS",
	"VCHLGS",
	"VCLZ",
	"VCLZB",
	"VCLZH",
	"VCLZF",
	"VCLZG",
	"VCTZ",
	"VCTZB",
	"VCTZH",
	"VCTZF",
	"VCTZG",
	"VEC",
	"VECB",
	"VECH",
	"VECF",
	"VECG",
	"VECL",
	"VECLB",
	"VECLH",
	"VECLF",

			opset(AVSRAH, r0)
			opset(AVSRAW, r0)
			opset(AVSRAD, r0)

		case AVSOI: /* vsldoi */
			opset(AVSLDOI, r0)

		case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */
			opset(AVCLZB, r0)
			opset(AVCLZH, r0)
			opset(AVCLZW, r0)
			opset(AVCLZD, r0)

		case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */
			opset(AVPOPCNTB, r0)
			opset(AVPOPCNTH, r0)
			opset(AVPOPCNTW, r0)

	// 386:"BSFL"
	// arm:"CLZ"
	// arm64:"RBITW","CLZW"
	// s390x:"FLOGR","MOVWZ"
	// ppc64x/power8:"ANDN","POPCNTW"
	// ppc64x/power9: "CNTTZW"
	// wasm:"I64Ctz"
	return bits.TrailingZeros32(n)
}

func TrailingZeros16(n uint16) int {
	// amd64:"BSFL","ORL\\t\\$65536"
	// 386:"BSFL\t"
	// arm:"ORR\t\\$65536","CLZ",-"MOVHU\tR"
	// arm64:"ORR\t\\$65536","RBITW","CLZW",-"MOVHU\tR",-"RBIT\t",-"CLZ\t"

	"DRET",
	"WFI",
	"SFENCEVMA",
	"ADDUW",
	"SH1ADD",
	"SH1ADDUW",
	"SH2ADD",
	"SH2ADDUW",
	"SH3ADD",
	"SH3ADDUW",
	"SLLIUW",
	"ANDN",
	"ORN",
	"XNOR",
	"CLZ",
	"CLZW",
	"CTZ",
	"CTZW",
	"CPOP",
	"CPOPW",
	"MAX",
	"MAXU",
	"MIN",
	"MINU",
	"SEXTB",
	"SEXTH",
	"ZEXTH",
	"ROL",
	"ROLW",
	"ROR",
	"RORI",
	"RORIW",
	"RORW",

// Separators with lengths of 2, 3 or 4 are handled
// specially.

// This works on power8 and above. The loads and
// compares are done in big endian order
// since that allows the used of VCLZD, and allows
// the same implementation to work on big and little
// endian platforms with minimal conditional changes.

// NOTE: There is a power9 implementation that
// improves performance by 10-15% on little

	"CASPW",
	"CASW",
	"CBNZ",
	"CBNZW",
	"CBZ",
	"CBZW",
	"CCMN",
	"CCMNW",
	"CCMP",
	"CCMPW",
	"CINC",
	"CINCW",
	"CINV",
	"CINVW",
	"CLREX",
	"CLS",
	"CLSW",
	"CLZ",
	"CLZW",
	"CMN",
	"CMNW",
	"CMP",
	"CMPW",
	"CNEG",
	"CNEGW",
	"CRC32B",
	"CRC32CB",
	"CRC32CH",
	"CRC32CW",
	"CRC32CX",
	"CRC32H",
	"CRC32W",
	"CRC32X",
	"CSEL",
	"CSELW",
	"CSET",

	// arm64:"MADDW",-"MOVWU"
	ret += uint64(t3*t4 + t2)

	// arm64:"REVW",-"MOVWU"
	ret += uint64(bits.ReverseBytes32(t1))

	// arm64:"RBITW",-"MOVWU"
	ret += uint64(bits.Reverse32(t1))

	// arm64:"CLZW",-"MOVWU"
	ret += uint64(bits.LeadingZeros32(t1))

	// arm64:"REV16W",-"MOVWU"
	ret += uint64(((t1 & 0xff00ff00) >> 8) | ((t1 & 0x00ff00ff) << 8))

	// arm64:"EXTRW",-"MOVWU"