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Results 1 - 10 of 11 for CMNW (0.25 sec)

  1. test/codegen/comparisons.go

    	// amd64:`TESTL`,-`ANDL`
    	c0 := a&b < 0
    	// arm:`CMN`,-`ADD`
    	// arm64:`CMNW`,-`ADD`
    	c1 := a+b < 0
    	// arm:`TEQ`,-`XOR`
    	c2 := a^b < 0
    	// arm64:`TST`,-`AND`
    	// amd64:`TESTQ`,-`ANDQ`
    	c3 := e&f < 0
    	// arm64:`CMN`,-`ADD`
    	c4 := e+f < 0
    	// not optimized to single CMNW/CMN due to further use of b+d
    	// arm64:`ADD`,-`CMNW`
    	// arm:`ADD`,-`CMN`
    	c5 := b+d == 0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 19 16:31:02 UTC 2024
    - 15.2K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules

    (CMPWconst [c] x) && !isARM64addcon(int64(c))  => (CMPW x (MOVDconst [int64(c)]))
    (CMNconst [c] x) && !isARM64addcon(c)  => (CMN x (MOVDconst [c]))
    (CMNWconst [c] x) && !isARM64addcon(int64(c))  => (CMNW x (MOVDconst [int64(c)]))
    
    (ADDSconstflags [c] x) && !isARM64addcon(c)  => (ADDSflags x (MOVDconst [c]))
    
    // These rules remove unneeded sign/zero extensions.
    // They occur in late lower because they rely on the fact
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 4.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/arm64/anames.go

    	"CBNZ",
    	"CBNZW",
    	"CBZ",
    	"CBZW",
    	"CCMN",
    	"CCMNW",
    	"CCMP",
    	"CCMPW",
    	"CINC",
    	"CINCW",
    	"CINV",
    	"CINVW",
    	"CLREX",
    	"CLS",
    	"CLSW",
    	"CLZ",
    	"CLZW",
    	"CMN",
    	"CMNW",
    	"CMP",
    	"CMPW",
    	"CNEG",
    	"CNEGW",
    	"CRC32B",
    	"CRC32CB",
    	"CRC32CH",
    	"CRC32CW",
    	"CRC32CX",
    	"CRC32H",
    	"CRC32W",
    	"CRC32X",
    	"CSEL",
    	"CSELW",
    	"CSET",
    	"CSETM",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	CLZ R21, R9                                // a912c0da
    	CMNW R21.UXTB<<4, R15                      // ff11352b
    	CMN R0.UXTW<<4, R16                        // 1f5220ab
    	CMNW R13>>8, R9                            // 3f214d2b
    	CMN R6->17, R3                             // 7f4486ab
    	CMNW $(2<<12), R5                          // CMNW $8192, R5                // bf084031
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    // CMP(x,-y) -> CMN(x,y) is only valid for unordered comparison, if y can be -1<<63
    ((EQ|NE) (CMP x z:(NEG y)) yes no)   && z.Uses == 1 => ((EQ|NE) (CMN x y) yes no)
    ((Equal|NotEqual) (CMP x z:(NEG y))) && z.Uses == 1 => ((Equal|NotEqual) (CMN x y))
    
    // CMPW(x,-y) -> CMNW(x,y) is only valid for unordered comparison, if y can be -1<<31
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/rewriteARM64latelower.go

    }
    func rewriteValueARM64latelower_OpARM64CMNWconst(v *Value) bool {
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (CMNWconst [c] x)
    	// cond: !isARM64addcon(int64(c))
    	// result: (CMNW x (MOVDconst [int64(c)]))
    	for {
    		c := auxIntToInt32(v.AuxInt)
    		x := v_0
    		if !(!isARM64addcon(int64(c))) {
    			break
    		}
    		v.reset(OpARM64CMNW)
    		v0 := b.NewValue0(v.Pos, OpARM64MOVDconst, typ.UInt64)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 12 19:38:41 UTC 2024
    - 19.3K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "CMNconst", argLength: 1, reg: gp1flags, asm: "CMN", aux: "Int64", typ: "Flags"},   // arg0 compare to -auxInt
    		{name: "CMNW", argLength: 2, reg: gp2flags, asm: "CMNW", typ: "Flags", commutative: true}, // arg0 compare to -arg1, 32 bit, provided arg1 is not 1<<31
    		{name: "CMNWconst", argLength: 1, reg: gp1flags, asm: "CMNW", aux: "Int32", typ: "Flags"}, // arg0 compare to -auxInt, 32 bit
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/arm64.s

    	CMPW	$40960, R0                      // 1f284071
    	CMPW	$27745, R2                      // 3b8c8d525f001b6b
    	CMNW	$0x3fffffc0, R2                 // CMNW	$1073741760, R2                   // fb5f1a325f001b2b
    	CMPW	$0xffff0, R1                    // CMPW	$1048560, R1                      // fb3f1c323f001b6b
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteARM64.go

    			v.AddArg2(x0, y)
    			return true
    		}
    		break
    	}
    	return false
    }
    func rewriteValueARM64_OpARM64CMNW(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (CMNW x (MOVDconst [c]))
    	// result: (CMNWconst [int32(c)] x)
    	for {
    		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
    			x := v_0
    			if v_1.Op != OpARM64MOVDconst {
    				continue
    			}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 608.6K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/arm64error.s

    	CMPW	R7@>2, R5                                        // ERROR "unsupported shift operator"
    	CMN	R7@>2, R5                                        // ERROR "unsupported shift operator"
    	CMNW	R7@>2, R5                                        // ERROR "unsupported shift operator"
    	NEG	R7@>2, R5                                        // ERROR "unsupported shift operator"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
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