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Results 1 - 5 of 5 for EXTRW (0.07 sec)

  1. test/codegen/bitfield.go

    	return x<<7 ^ x2>>57 // arm64:"EXTR\t[$]57,"
    }
    
    func extr4(x, x2 uint32) uint32 {
    	return x<<7 + x2>>25 // arm64:"EXTRW\t[$]25,"
    }
    
    func extr5(x, x2 uint32) uint32 {
    	return x<<7 | x2>>25 // arm64:"EXTRW\t[$]25,"
    }
    
    func extr6(x, x2 uint32) uint32 {
    	return x<<7 ^ x2>>25 // arm64:"EXTRW\t[$]25,"
    }
    
    // check 32-bit shift masking
    func mask32(x uint32) uint32 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 23 06:11:32 UTC 2022
    - 9.6K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/arm64/anames.go

    	"CSINVW",
    	"CSNEG",
    	"CSNEGW",
    	"DC",
    	"DCPS1",
    	"DCPS2",
    	"DCPS3",
    	"DMB",
    	"DRPS",
    	"DSB",
    	"DWORD",
    	"EON",
    	"EONW",
    	"EOR",
    	"EORW",
    	"ERET",
    	"EXTR",
    	"EXTRW",
    	"FABSD",
    	"FABSS",
    	"FADDD",
    	"FADDS",
    	"FCCMPD",
    	"FCCMPED",
    	"FCCMPES",
    	"FCCMPS",
    	"FCMPD",
    	"FCMPED",
    	"FCMPES",
    	"FCMPS",
    	"FCSELD",
    	"FCSELS",
    	"FCVTDH",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  3. test/codegen/noextend.go

    	// arm64:"CLZW",-"MOVWU"
    	ret += uint64(bits.LeadingZeros32(t1))
    
    	// arm64:"REV16W",-"MOVWU"
    	ret += uint64(((t1 & 0xff00ff00) >> 8) | ((t1 & 0x00ff00ff) << 8))
    
    	// arm64:"EXTRW",-"MOVWU"
    	ret += uint64((t1 << 25) | (t2 >> 7))
    
    	return ret
    }
    
    // no sign extension when the upper bits of the result are zero
    
    func noSignEXT(x int) int64 {
    	t1 := int32(x)
    
    	var ret int64
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Dec 14 17:22:18 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	EOR $-2287828610704211969, R27, R22        // 76e343d2
    	EORW R12->27, R10, R19                     // 536d8c4a
    	EOR R2<<59, R30, R17                       // d1ef02ca
    	ERET                                       // e0039fd6
    	EXTRW $7, R8, R10, R25                     // 591d8813
    	EXTR $35, R22, R12, R8                     // 888dd693
    	SEVL                                       // bf2003d5
    	HINT $6                                    // df2003d5
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "EXTRconst", argLength: 2, reg: gp21, asm: "EXTR", aux: "Int64"},   // extract 64 bits from arg0:arg1 starting at lsb auxInt, auxInt should be in the range 0 to 63.
    		{name: "EXTRWconst", argLength: 2, reg: gp21, asm: "EXTRW", aux: "Int64"}, // extract 32 bits from arg0[31:0]:arg1[31:0] starting at lsb auxInt and zero top 32 bits, auxInt should be in the range 0 to 31.
    
    		// comparisons
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
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