TEXT ·archExp(SB),$0-16
	FMOVD	x+0(FP), F0	// F0 = x
	FCMPD	F0, F0
	BNE	isNaN		// x = NaN, return NaN
	FMOVD	$Overflow, F1
	FCMPD	F1, F0
	BGT	overflow	// x > Overflow, return PosInf
	FMOVD	$Underflow, F1
	FCMPD	F1, F0
	BLT	underflow	// x < Underflow, return 0
	MOVD	$NearZero, R0
	FMOVD	R0, F2
	FABSD	F0, F3
	FMOVD	$1.0, F1	// F1 = 1.0
	FCMPD	F2, F3
	BLT	nearzero	// fabs(x) < NearZero, return 1 + x

	"DWORD",
	"EON",
	"EONW",
	"EOR",
	"EORW",
	"ERET",
	"EXTR",
	"EXTRW",
	"FABSD",
	"FABSS",
	"FADDD",
	"FADDS",
	"FCCMPD",
	"FCCMPED",
	"FCCMPES",
	"FCCMPS",
	"FCMPD",
	"FCMPED",
	"FCMPES",
	"FCMPS",
	"FCSELD",
	"FCSELS",
	"FCVTDH",
	"FCVTDS",
	"FCVTHD",
	"FCVTHS",
	"FCVTSD",
	"FCVTSH",
	"FCVTZSD",
	"FCVTZSDW",
	"FCVTZSS",
	"FCVTZSSW",

	// riscv64:"FMSUBD\t"
	return x*y - z
}

func FusedSub64_b(x, y, z float64) float64 {
	// arm64:"FMSUBD"
	// riscv64:"FNMSUBD\t"
	return z - x*y
}

func Cmp(f float64) bool {
	// arm64:"FCMPD","(BGT|BLE|BMI|BPL)",-"CSET\tGT",-"CBZ"
	return f > 4 || f < -4
}

func CmpZero64(f float64) bool {
	// s390x:"LTDBR",-"FCMPU"
	return f <= 0
}

func CmpZero32(f float32) bool {

using different register names.

Examples:

	ADC R24, R14, R12          <=>     adc x12, x14, x24
	ADDW R26->24, R21, R15     <=>     add w15, w21, w26, asr #24
	FCMPS F2, F3               <=>     fcmp s3, s2
	FCMPD F2, F3               <=>     fcmp d3, d2
	FCVTDH F2, F3              <=>     fcvt h3, d2

2. Go uses .P and .W suffixes to indicate post-increment and pre-increment.

Examples:

	//TODO VFCMLT $0, V8.S4, V7.S4             // 07e9a04e
	FCMPS F3, F17                              // 2022231e
	FCMPS $(0.0), F8                           // 0821201e
	FCMPD F11, F27                             // 60236b1e
	FCMPD $(0.0), F25                          // 2823601e
	FCMPES F16, F30                            // d023301e
	FCMPES $(0.0), F29                         // b823201e

		{name: "FCMPD", argLength: 2, reg: fp2flags, asm: "FCMPD", typ: "Flags"},                  // arg0 compare to arg1, float64
		{name: "FCMPS0", argLength: 1, reg: fp1flags, asm: "FCMPS", typ: "Flags"},                 // arg0 compare to 0, float32
		{name: "FCMPD0", argLength: 1, reg: fp1flags, asm: "FCMPD", typ: "Flags"},                 // arg0 compare to 0, float64

		// shifted ops

// Optimize comparison between a floating-point value and 0.0 with "FCMP $(0.0), Fn"
(FCMPS x (FMOVSconst [0])) => (FCMPS0 x)
(FCMPS (FMOVSconst [0]) x) => (InvertFlags (FCMPS0 x))
(FCMPD x (FMOVDconst [0])) => (FCMPD0 x)
(FCMPD (FMOVDconst [0]) x) => (InvertFlags (FCMPD0 x))

// CSEL needs a flag-generating argument. Synthesize a TSTW if necessary.

	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (FCMPD x (FMOVDconst [0]))
	// result: (FCMPD0 x)
	for {
		x := v_0
		if v_1.Op != OpARM64FMOVDconst || auxIntToFloat64(v_1.AuxInt) != 0 {
			break
		}
		v.reset(OpARM64FCMPD0)
		v.AddArg(x)
		return true
	}
	// match: (FCMPD (FMOVDconst [0]) x)
	// result: (InvertFlags (FCMPD0 x))
	for {

				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FCMPD",
		argLen: 2,
		asm:    arm64.AFCMPD,
		reg: regInfo{
			inputs: []inputInfo{