FCMPD	$0.0, F0
	FCSELD	LT, F4, F3, F3	// F3 = k
	FCVTZSD	F3, R1		// R1 = int(k)
	SCVTFD	R1, F3		// F3 = float64(int(k))
	FMOVD	$Ln2Hi, F4	// F4 = Ln2Hi
	FMOVD	$Ln2Lo, F5	// F5 = Ln2Lo
	FMSUBD	F3, F0, F4, F4	// F4 = hi = x - float64(int(k))*Ln2Hi
	FMULD	F3, F5		// F5 = lo = float64(int(k)) * Ln2Lo
	FSUBD	F5, F4, F6	// F6 = r = hi - lo
	FMULD	F6, F6, F7	// F7 = t = r * r
	// compute y
	FMOVD	$P5, F8		// F8 = P5

	// riscv64:"FMADDD\t"
	return x*y + z
}

func FusedSub64_a(x, y, z float64) float64 {
	// s390x:"FMSUB\t"
	// ppc64x:"FMSUB\t"
	// riscv64:"FMSUBD\t"
	return x*y - z
}

func FusedSub64_b(x, y, z float64) float64 {
	// arm64:"FMSUBD"
	// riscv64:"FNMSUBD\t"
	return z - x*y
}

func Cmp(f float64) bool {
	// arm64:"FCMPD","(BGT|BLE|BMI|BPL)",-"CSET\tGT",-"CBZ"
	return f > 4 || f < -4

	"FMVXW",
	"FMVWX",
	"FEQS",
	"FLTS",
	"FLES",
	"FCLASSS",
	"FLD",
	"FSD",
	"FADDD",
	"FSUBD",
	"FMULD",
	"FDIVD",
	"FMIND",
	"FMAXD",
	"FSQRTD",
	"FMADDD",
	"FMSUBD",
	"FNMADDD",
	"FNMSUBD",
	"FCVTWD",
	"FCVTLD",
	"FCVTDW",
	"FCVTDL",
	"FCVTWUD",
	"FCVTLUD",
	"FCVTDWU",
	"FCVTDLU",
	"FCVTSD",
	"FCVTDS",
	"FSGNJD",
	"FSGNJND",

	"FLDPQ",
	"FLDPS",
	"FMADDD",
	"FMADDS",
	"FMAXD",
	"FMAXNMD",
	"FMAXNMS",
	"FMAXS",
	"FMIND",
	"FMINNMD",
	"FMINNMS",
	"FMINS",
	"FMOVD",
	"FMOVQ",
	"FMOVS",
	"FMSUBD",
	"FMSUBS",
	"FMULD",
	"FMULS",
	"FNEGD",
	"FNEGS",
	"FNMADDD",
	"FNMADDS",
	"FNMSUBD",
	"FNMSUBS",
	"FNMULD",
	"FNMULS",
	"FRINTAD",
	"FRINTAS",
	"FRINTID",
	"FRINTIS",

	// arm/6:"FMULAD"
	// arm64:"FMADDD"
	// s390x:"FMADD"
	// ppc64x:"FMADD"
	// riscv64:"FMADDD"
	return math.FMA(x, y, z)
}

func fms(x, y, z float64) float64 {
	// riscv64:"FMSUBD"
	return math.FMA(x, y, -z)
}

func fnms(x, y, z float64) float64 {
	// riscv64:"FNMSUBD",-"FNMADDD"
	return math.FMA(-x, y, z)
}

func fnma(x, y, z float64) float64 {

Examples:

	MADD R2, R30, R22, R6       <=>    madd x6, x22, x2, x30
	SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3

(3) FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS <Fm>, <Fa>, <Fn>, <Fd>

Examples:

	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25

		{name: "FMADDD", argLength: 3, reg: fp31, asm: "FMADDD", commutative: true, typ: "Float64"},                                         // (arg0 * arg1) + arg2
		{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD", commutative: true, typ: "Float64"},                                         // (arg0 * arg1) - arg2

	FSGNJD	F1, F0, F2				// 53011022
	FSGNJND	F1, F0, F2				// 53111022
	FSGNJXD	F1, F0, F2				// 53211022
	FMVXD	F0, X5					// d30200e2
	FMVDX	X5, F0					// 538002f2
	FMADDD	F1, F2, F3, F4				// 4382201a
	FMSUBD	F1, F2, F3, F4				// 4782201a
	FNMSUBD	F1, F2, F3, F4				// 4b82201a
	FNMADDD	F1, F2, F3, F4				// 4f82201a

	// 12.6: Double-Precision Floating-Point Classify Instruction
	FCLASSD	F0, X5					// d31200e2

		{name: "FNMADDD", argLength: 3, reg: fp31, asm: "FNMADDD"}, // -arg0 - (arg1 * arg2)
		{name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"},   // +arg0 - (arg1 * arg2)
		{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD"},   // +arg0 - (arg1 * arg2)
		{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2)
		{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2)

	FMOVD F2, F9                               // 4940601e
	FMOVS F4, F27                              // 9b40201e
	//TODO VFMOV $3.125, V8.D2                 // 28f5006f
	FMSUBS F13, F21, F13, F19                  // b3d50d1f
	FMSUBD F11, F7, F15, F31                   // ff9d4b1f
	//TODO VFMUL V9.S[2], F21, F19             // b39a895f
	//TODO VFMUL V26.S[2], V26.S2, V2.S2       // 429b9a0f
	//TODO VFMUL V21.D2, V17.D2, V25.D2        // 39de756e