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Results 1 - 10 of 17 for FNMSUBS (0.23 sec)

  1. src/cmd/internal/obj/riscv/anames.go

    	"FSFLAGS",
    	"FSRMI",
    	"FSFLAGSI",
    	"FLW",
    	"FSW",
    	"FADDS",
    	"FSUBS",
    	"FMULS",
    	"FDIVS",
    	"FMINS",
    	"FMAXS",
    	"FSQRTS",
    	"FMADDS",
    	"FMSUBS",
    	"FNMADDS",
    	"FNMSUBS",
    	"FCVTWS",
    	"FCVTLS",
    	"FCVTSW",
    	"FCVTSL",
    	"FCVTWUS",
    	"FCVTLUS",
    	"FCVTSWU",
    	"FCVTSLU",
    	"FSGNJS",
    	"FSGNJNS",
    	"FSGNJXS",
    	"FMVXS",
    	"FMVSX",
    	"FMVXW",
    	"FMVWX",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 2.9K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/arm64/anames.go

    	"FMINNMD",
    	"FMINNMS",
    	"FMINS",
    	"FMOVD",
    	"FMOVQ",
    	"FMOVS",
    	"FMSUBD",
    	"FMSUBS",
    	"FMULD",
    	"FMULS",
    	"FNEGD",
    	"FNEGS",
    	"FNMADDD",
    	"FNMADDS",
    	"FNMSUBD",
    	"FNMSUBS",
    	"FNMULD",
    	"FNMULS",
    	"FRINTAD",
    	"FRINTAS",
    	"FRINTID",
    	"FRINTIS",
    	"FRINTMD",
    	"FRINTMS",
    	"FRINTND",
    	"FRINTNS",
    	"FRINTPD",
    	"FRINTPS",
    	"FRINTXD",
    	"FRINTXS",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  3. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

    	return fmt.Sprintf("???(%v)", arg)
    }
    
    func reverseMiddleOps(op Op) bool {
    	switch op {
    	case FMADD, FMADDCC, FMADDS, FMADDSCC, FMSUB, FMSUBCC, FMSUBS, FMSUBSCC, FNMADD, FNMADDCC, FNMADDS, FNMADDSCC, FNMSUB, FNMSUBCC, FNMSUBS, FNMSUBSCC, FSEL, FSELCC:
    		return true
    	}
    	return false
    }
    
    func reverseOperandOrder(op Op) bool {
    	switch op {
    	// Special case for SUBF, SUBFC: not reversed
    	case ADD, ADDC, ADDE, ADDCC, ADDCCC:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 10.9K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/doc.go

    	SMSUBL R10, R3, R17, R27    <=>    smsubl x27, w17, w10, x3
    
    (3) FMADDD, FMADDS, FMSUBD, FMSUBS, FNMADDD, FNMADDS, FNMSUBD, FNMSUBS <Fm>, <Fa>, <Fn>, <Fd>
    
    Examples:
    
    	FMADDD F30, F20, F3, F29    <=>    fmadd d29, d3, d30, d20
    	FNMSUBS F7, F25, F7, F22    <=>    fnmsub s22, s7, s7, s25
    
    (4) BFI, BFXIL, SBFIZ, SBFX, UBFIZ, UBFX $<lsb>, <Rn>, $<width>, <Rd>
    
    Examples:
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Aug 07 00:21:42 UTC 2023
    - 9.6K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/ppc64/anames.go

    	"FMUL",
    	"FMULCC",
    	"FMULS",
    	"FMULSCC",
    	"FNABS",
    	"FNABSCC",
    	"FNEG",
    	"FNEGCC",
    	"FNMADD",
    	"FNMADDCC",
    	"FNMADDS",
    	"FNMADDSCC",
    	"FNMSUB",
    	"FNMSUBCC",
    	"FNMSUBS",
    	"FNMSUBSCC",
    	"FRSP",
    	"FRSPCC",
    	"FSUB",
    	"FSUBCC",
    	"FSUBS",
    	"FSUBSCC",
    	"ISEL",
    	"MOVMW",
    	"LBAR",
    	"LHAR",
    	"LSW",
    	"LWAR",
    	"LWSYNC",
    	"MOVDBR",
    	"MOVWBR",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Apr 01 18:50:29 UTC 2024
    - 6.7K bytes
    - Viewed (0)
  6. test/codegen/floats.go

    func FusedSub32_a(x, y, z float32) float32 {
    	// s390x:"FMSUBS\t"
    	// ppc64x:"FMSUBS\t"
    	// riscv64:"FMSUBS\t"
    	return x*y - z
    }
    
    func FusedSub32_b(x, y, z float32) float32 {
    	// arm64:"FMSUBS"
    	// riscv64:"FNMSUBS\t"
    	return z - x*y
    }
    
    func FusedAdd64(x, y, z float64) float64 {
    	// s390x:"FMADD\t"
    	// ppc64x:"FMADD\t"
    	// arm64:"FMADDD"
    	// riscv64:"FMADDD\t"
    	return x*y + z
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Apr 04 15:24:29 UTC 2024
    - 4.9K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/RISCV64Ops.go

    		{name: "FNMADDS", argLength: 3, reg: fp31, asm: "FNMADDS", commutative: true, typ: "Float32"},                                       // -(arg0 * arg1) + arg2
    		{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS", commutative: true, typ: "Float32"},                                       // -(arg0 * arg1) - arg2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 30.7K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/riscv64.s

    	FMVXS	F0, X5					// d30200e0
    	FMVSX	X5, F0					// 538002f0
    	FMVXW	F0, X5					// d30200e0
    	FMVWX	X5, F0					// 538002f0
    	FMADDS	F1, F2, F3, F4				// 43822018
    	FMSUBS	F1, F2, F3, F4				// 47822018
    	FNMSUBS	F1, F2, F3, F4				// 4b822018
    	FNMADDS	F1, F2, F3, F4				// 4f822018
    
    	// 11.8: Single-Precision Floating-Point Compare Instructions
    	FEQS	F0, F1, X7				// d3a300a0
    	FLTS	F0, F1, X7				// d39300a0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Mar 22 04:42:21 UTC 2024
    - 16.7K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"},   // +arg0 - (arg1 * arg2)
    		{name: "FMSUBD", argLength: 3, reg: fp31, asm: "FMSUBD"},   // +arg0 - (arg1 * arg2)
    		{name: "FNMSUBS", argLength: 3, reg: fp31, asm: "FNMSUBS"}, // -arg0 + (arg1 * arg2)
    		{name: "FNMSUBD", argLength: 3, reg: fp31, asm: "FNMSUBD"}, // -arg0 + (arg1 * arg2)
    		{name: "MADD", argLength: 3, reg: gp31, asm: "MADD"},       // +arg0 + (arg1 * arg2)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	FNEGS F16, F5                              // 0542211e
    	FNEGD F31, F31                             // ff43611e
    	FNMADDS F17, F22, F6, F20                  // d458311f
    	FNMADDD F15, F0, F26, F20                  // 54036f1f
    	FNMSUBS F14, F16, F27, F14                 // 6ec32e1f
    	FNMSUBD F29, F25, F8, F10                  // 0ae57d1f
    	FNMULS F24, F22, F18                       // d28a381e
    	FNMULD F14, F30, F7                        // c78b6e1e
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
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