FSQRTS	F0, F1					// d3000058

	// 11.7: Single-Precision Floating-Point Conversion and Move Instructions
	FCVTWS	F0, X5					// d31200c0
	FCVTWS.RNE	F0, X5				// d30200c0
	FCVTWS.RTZ	F0, X5				// d31200c0
	FCVTWS.RDN	F0, X5				// d32200c0
	FCVTWS.RUP	F0, X5				// d33200c0
	FCVTWS.RMM	F0, X5				// d34200c0
	FCVTLS	F0, X5					// d31220c0
	FCVTLS.RNE	F0, X5				// d30220c0
	FCVTLS.RTZ	F0, X5				// d31220c0

	"FSRMI",
	"FSFLAGSI",
	"FLW",
	"FSW",
	"FADDS",
	"FSUBS",
	"FMULS",
	"FDIVS",
	"FMINS",
	"FMAXS",
	"FSQRTS",
	"FMADDS",
	"FMSUBS",
	"FNMADDS",
	"FNMSUBS",
	"FCVTWS",
	"FCVTLS",
	"FCVTSW",
	"FCVTSL",
	"FCVTWUS",
	"FCVTLUS",
	"FCVTSWU",
	"FCVTSLU",
	"FSGNJS",
	"FSGNJNS",
	"FSGNJXS",
	"FMVXS",
	"FMVSX",
	"FMVXW",
	"FMVWX",
	"FEQS",

		{name: "FCVTSL", argLength: 1, reg: gpfp, asm: "FCVTSL", typ: "Float32"},                                                            // float32(arg0)
		{name: "FCVTWS", argLength: 1, reg: fpgp, asm: "FCVTWS", typ: "Int32"},                                                              // int32(arg0)

(ZeroExt32to64 ...) => (MOVWUreg ...)

(Cvt32to32F ...) => (FCVTSW ...)
(Cvt32to64F ...) => (FCVTDW ...)
(Cvt64to32F ...) => (FCVTSL ...)
(Cvt64to64F ...) => (FCVTDL ...)

(Cvt32Fto32 ...) => (FCVTWS ...)
(Cvt32Fto64 ...) => (FCVTLS ...)
(Cvt64Fto32 ...) => (FCVTWD ...)
(Cvt64Fto64 ...) => (FCVTLD ...)

(Cvt32Fto64F ...) => (FCVTDS ...)
(Cvt64Fto32F ...) => (FCVTSD ...)

				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FCVTWS",
		argLen: 1,
		asm:    riscv.AFCVTWS,
		reg: regInfo{
			inputs: []inputInfo{