"FSW",
	"FADDS",
	"FSUBS",
	"FMULS",
	"FDIVS",
	"FMINS",
	"FMAXS",
	"FSQRTS",
	"FMADDS",
	"FMSUBS",
	"FNMADDS",
	"FNMSUBS",
	"FCVTWS",
	"FCVTLS",
	"FCVTSW",
	"FCVTSL",
	"FCVTWUS",
	"FCVTLUS",
	"FCVTSWU",
	"FCVTSLU",
	"FSGNJS",
	"FSGNJNS",
	"FSGNJXS",
	"FMVXS",
	"FMVSX",
	"FMVXW",
	"FMVWX",
	"FEQS",
	"FLTS",
	"FLES",
	"FCLASSS",

		{name: "FCVTSW", argLength: 1, reg: gpfp, asm: "FCVTSW", typ: "Float32"},                                                            // float32(low 32 bits of arg0)
		{name: "FCVTSL", argLength: 1, reg: gpfp, asm: "FCVTSL", typ: "Float32"},                                                            // float32(arg0)

	FCVTLS.RNE	F0, X5				// d30220c0
	FCVTLS.RTZ	F0, X5				// d31220c0
	FCVTLS.RDN	F0, X5				// d32220c0
	FCVTLS.RUP	F0, X5				// d33220c0
	FCVTLS.RMM	F0, X5				// d34220c0
	FCVTSW	X5, F0					// 538002d0
	FCVTSL	X5, F0					// 538022d0
	FCVTWUS	F0, X5					// d31210c0
	FCVTWUS.RNE	F0, X5				// d30210c0
	FCVTWUS.RTZ	F0, X5				// d31210c0
	FCVTWUS.RDN	F0, X5				// d32210c0
	FCVTWUS.RUP	F0, X5				// d33210c0

(ZeroExt16to32 ...) => (MOVHUreg ...)
(ZeroExt16to64 ...) => (MOVHUreg ...)
(ZeroExt32to64 ...) => (MOVWUreg ...)

(Cvt32to32F ...) => (FCVTSW ...)
(Cvt32to64F ...) => (FCVTDW ...)
(Cvt64to32F ...) => (FCVTSL ...)
(Cvt64to64F ...) => (FCVTDL ...)

(Cvt32Fto32 ...) => (FCVTWS ...)
(Cvt32Fto64 ...) => (FCVTLS ...)
(Cvt64Fto32 ...) => (FCVTWD ...)
(Cvt64Fto64 ...) => (FCVTLD ...)

(Cvt32Fto64F ...) => (FCVTDS ...)

				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
			},
		},
	},
	{
		name:   "FCVTSL",
		argLen: 1,
		asm:    riscv.AFCVTSL,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30