"BINV",
	"BINVI",
	"BSET",
	"BSETI",
	"WORD",
	"BEQZ",
	"BGEZ",
	"BGT",
	"BGTU",
	"BGTZ",
	"BLE",
	"BLEU",
	"BLEZ",
	"BLTZ",
	"BNEZ",
	"FABSD",
	"FABSS",
	"FNEGD",
	"FNEGS",
	"FNED",
	"FNES",
	"MOV",
	"MOVB",
	"MOVBU",
	"MOVF",
	"MOVD",
	"MOVH",
	"MOVHU",
	"MOVW",
	"MOVWU",
	"NEG",
	"NEGW",
	"NOT",
	"SEQZ",
	"SNEZ",

	"FMAXD",
	"FMAXNMD",
	"FMAXNMS",
	"FMAXS",
	"FMIND",
	"FMINNMD",
	"FMINNMS",
	"FMINS",
	"FMOVD",
	"FMOVQ",
	"FMOVS",
	"FMSUBD",
	"FMSUBS",
	"FMULD",
	"FMULS",
	"FNEGD",
	"FNEGS",
	"FNMADDD",
	"FNMADDS",
	"FNMSUBD",
	"FNMSUBS",
	"FNMULD",
	"FNMULS",
	"FRINTAD",
	"FRINTAS",
	"FRINTID",
	"FRINTIS",
	"FRINTMD",
	"FRINTMS",
	"FRINTND",

		{name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD", typ: "Float64"},                                                            // sqrt(arg0)
		{name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD", typ: "Float64"},                                                              // -arg0

	SNEZ	X15, X15				// b337f000

	// F extension
	FABSS	F0, F1					// d3200020
	FNEGS	F0, F1					// d3100020
	FNES	F0, F1, X7				// d3a300a093c31300

	// D extension
	FABSD	F0, F1					// d3200022
	FNEGD	F0, F1					// d3100022
	FNED	F0, F1, X5				// d3a200a293c21200
	FLTD	F0, F1, X5				// d39200a2
	FLED	F0, F1, X5				// d38200a2
	FEQD	F0, F1, X5				// d3a200a2

(F(MADD|NMADD|MSUB|NMSUB)S x y neg:(FNEGS z)) && neg.Uses == 1 => (F(MSUB|NMSUB|MADD|NMADD)S x y z)
(F(MADD|NMADD|MSUB|NMSUB)D neg:(FNEGD x) y z) && neg.Uses == 1 => (F(NMSUB|MSUB|NMADD|MADD)D x y z)

			return true
		}
		break
	}
	return false
}
func rewriteValueRISCV64_OpRISCV64FMADDD(v *Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (FMADDD neg:(FNEGD x) y z)
	// cond: neg.Uses == 1
	// result: (FNMSUBD x y z)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			neg := v_0
			if neg.Op != OpRISCV64FNEGD {
				continue
			}

		{name: "FNEGS", argLength: 1, reg: fp11, asm: "FNEGS"},                                // -arg0, float32
		{name: "FNEGD", argLength: 1, reg: fp11, asm: "FNEGD"},                                // -arg0, float64
		{name: "FSQRTD", argLength: 1, reg: fp11, asm: "FSQRTD"},                              // sqrt(arg0), float64

// FP simplification
(FNEGS  (FMULS  x y)) => (FNMULS x y)
(FNEGD  (FMULD  x y)) => (FNMULD x y)
(FMULS  (FNEGS  x) y) => (FNMULS x y)
(FMULD  (FNEGD  x) y) => (FNMULD x y)
(FNEGS  (FNMULS x y)) => (FMULS  x y)
(FNEGD  (FNMULD x y)) => (FMULD  x y)
(FNMULS (FNEGS  x) y) => (FMULS  x y)
(FNMULD (FNEGD  x) y) => (FMULD  x y)

(FADDS a (FMULS  x y)) && a.Block.Func.useFMA(v) => (FMADDS  a x y)

	//TODO FMULX F16, F1, F31                  // 3fdc705e
	//TODO VFMULX V29.S2, V13.S2, V31.S2       // bfdd3d0e
	//TODO VFNEG V18.S2, V12.S2                // 4cfaa02e
	FNEGS F16, F5                              // 0542211e
	FNEGD F31, F31                             // ff43611e
	FNMADDS F17, F22, F6, F20                  // d458311f
	FNMADDD F15, F0, F26, F20                  // 54036f1f
	FNMSUBS F14, F16, F27, F14                 // 6ec32e1f

		ins.as = AFSGNJXD
		ins.rs1 = uint32(p.From.Reg)

	case AFNEGS:
		// FNEGS rs, rd -> FSGNJNS rs, rs, rd
		ins.as = AFSGNJNS
		ins.rs1 = uint32(p.From.Reg)

	case AFNEGD:
		// FNEGD rs, rd -> FSGNJND rs, rs, rd
		ins.as = AFSGNJND
		ins.rs1 = uint32(p.From.Reg)

	case AROL, AROLW, AROR, ARORW:
		inss = instructionsForRotate(p, ins)

	case ARORI: