(BGE cond (MOVDconst [0]) yes no) => (BGEZ cond yes no)

// Remove redundant NEG from SEQZ/SNEZ.
(SEQZ (NEG x)) => (SEQZ x)
(SNEZ (NEG x)) => (SNEZ x)

// Remove redundant SEQZ/SNEZ.
(SEQZ (SEQZ x)) => (SNEZ x)
(SEQZ (SNEZ x)) => (SEQZ x)
(SNEZ (SEQZ x)) => (SEQZ x)
(SNEZ (SNEZ x)) => (SNEZ x)

// Store zero.

	"FABSS",
	"FNEGD",
	"FNEGS",
	"FNED",
	"FNES",
	"MOV",
	"MOVB",
	"MOVBU",
	"MOVF",
	"MOVD",
	"MOVH",
	"MOVHU",
	"MOVW",
	"MOVWU",
	"NEG",
	"NEGW",
	"NOT",
	"SEQZ",
	"SNEZ",
	"LAST",

		{name: "XORI", argLength: 1, reg: gp11, asm: "XORI", aux: "Int64"},    // arg0 ^ auxint

		// Generate boolean values
		{name: "SEQZ", argLength: 1, reg: gp11, asm: "SEQZ"},                 // arg0 == 0, result is 0 or 1
		{name: "SNEZ", argLength: 1, reg: gp11, asm: "SNEZ"},                 // arg0 != 0, result is 0 or 1

	return false
}
func rewriteValueRISCV64_OpRISCV64SEQZ(v *Value) bool {
	v_0 := v.Args[0]
	// match: (SEQZ (NEG x))
	// result: (SEQZ x)
	for {
		if v_0.Op != OpRISCV64NEG {
			break
		}
		x := v_0.Args[0]
		v.reset(OpRISCV64SEQZ)
		v.AddArg(x)
		return true
	}
	// match: (SEQZ (SEQZ x))
	// result: (SNEZ x)
	for {
		if v_0.Op != OpRISCV64SEQZ {
			break
		}

	BLE	X5, X6, 2(PC)				// 63545300
	BLEU	X5, X6, 2(PC)				// 63745300
	BLEZ	X5, 2(PC)				// 63545000
	BLTZ	X5, 2(PC)				// 63c40200
	BNEZ	X5, 2(PC)				// 63940200

	// Set pseudo-instructions
	SEQZ	X15, X15				// 93b71700
	SNEZ	X15, X15				// b337f000

	// F extension
	FABSS	F0, F1					// d3200020
	FNEGS	F0, F1					// d3100020
	FNES	F0, F1, X7				// d3a300a093c31300

	// D extension

		ins.as = AXORI
		ins.rs1, ins.rs2 = uint32(p.From.Reg), obj.REG_NONE
		if ins.rd == obj.REG_NONE {
			ins.rd = ins.rs1
		}
		ins.imm = -1

	case ASEQZ:
		// SEQZ rs, rd -> SLTIU $1, rs, rd
		ins.as = ASLTIU
		ins.rs1, ins.rs2 = uint32(p.From.Reg), obj.REG_NONE
		ins.imm = 1

	case ASNEZ:
		// SNEZ rs, rd -> SLTU rs, x0, rd
		ins.as = ASLTU

			},
			outputs: []outputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "SEQZ",
		argLen: 1,
		asm:    riscv.ASEQZ,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},