VSHASIGMAD	$15, e, $1, S1; \
	VADDUDM		xi, h, h; \
	VSHASIGMAD	$0, a, $1, S0; \
	VSHASIGMAD	$15, xj_14, $0, s1; \
	VADDUDM		FUNC, h, h; \
	VXOR		b, a, FUNC; \
	VADDUDM		xj_9, xj, xj; \
	VADDUDM		S1, h, h; \
	VSEL		b, c, FUNC, FUNC; \
	VADDUDM		KI, g, g; \
	VADDUDM		h, d, d; \
	VADDUDM		FUNC, S0, S0; \
	VADDUDM		s0, xj, xj; \
	LVX		(TBL)(idx), KI; \
	VADDUDM		S0, h, h; \
	VADDUDM		s1, xj, xj

	"VNAND",
	"VOR",
	"VORC",
	"VNOR",
	"VXOR",
	"VEQV",
	"VADDUM",
	"VADDUBM",
	"VADDUHM",
	"VADDUWM",
	"VADDUDM",
	"VADDUQM",
	"VADDCU",
	"VADDCUQ",
	"VADDCUW",
	"VADDUS",
	"VADDUBS",
	"VADDUHS",
	"VADDUWS",
	"VADDSS",
	"VADDSBS",
	"VADDSHS",
	"VADDSWS",
	"VADDE",
	"VADDEUQM",
	"VADDECUQ",
	"VSUBUM",
	"VSUBUBM",
	"VSUBUHM",
	"VSUBUWM",

	VCMPEQUB V0, V1, V0
	VPOPCNTD V2, V2		// A match is 0xFF or 0. Count the bits into doubleword buckets.
	VPOPCNTD V0, V0
	VADDUDM	V0, V4, V4	// Accumulate the popcounts. They are 8x the count.
	VADDUDM	V2, V5, V5	// The count will be fixed up afterwards.
	ADD	$32, R3
	BDNZ	cmploop

	VADDUDM	V4, V5, V5
	MFVSRD	V5, R18
	VSLDOI	$8, V5, V5, V5
	MFVSRD	V5, R21
	ADD	R21, R18, R18
	ANDCC	$31, R4, R4

	VADDCUQ  T0, RED1, CAR1     // VACCQ
	VADDUQM  T0, RED1, T0       // VAQ
	VADDECUQ T1, RED2, CAR1, T2 // VACCCQ
	VADDEUQM T1, RED2, CAR1, T1 // VACQ

	VADDCUQ  T0, ADD3, CAR1       // VACCQ
	VADDUQM  T0, ADD3, T0         // VAQ
	VADDECUQ T1, ADD4, CAR1, CAR2 // VACCCQ
	VADDEUQM T1, ADD4, CAR1, T1   // VACQ
	VADDUQM  T2, CAR2, T2         // VAQ

	LXVD2X  (R18)(CPOOL), SEL2

	VEQV V1, V2, V3                 // 10611684
	VADDUBM V1, V2, V3              // 10611000
	VADDUHM V1, V2, V3              // 10611040
	VADDUWM V1, V2, V3              // 10611080
	VADDUDM V1, V2, V3              // 106110c0
	VADDUQM V1, V2, V3              // 10611100
	VADDCUQ V1, V2, V3              // 10611140
	VADDCUW V1, V2, V3              // 10611180
	VADDUBS V1, V2, V3              // 10611200

	VADDFP:         "vaddfp",
	VADDSBS:        "vaddsbs",
	VADDSHS:        "vaddshs",
	VADDSWS:        "vaddsws",
	VADDUBM:        "vaddubm",
	VADDUBS:        "vaddubs",
	VADDUHM:        "vadduhm",
	VADDUHS:        "vadduhs",
	VADDUWM:        "vadduwm",
	VADDUWS:        "vadduws",
	VAND:           "vand",
	VANDC:          "vandc",
	VAVGSB:         "vavgsb",
	VAVGSH:         "vavgsh",

			opset(AVEQV, r0)

		case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */
			opset(AVADDUBM, r0)
			opset(AVADDUHM, r0)
			opset(AVADDUWM, r0)
			opset(AVADDUDM, r0)
			opset(AVADDUQM, r0)

		case AVADDCU: /* vaddcuq, vaddcuw */
			opset(AVADDCUQ, r0)
			opset(AVADDCUW, r0)

		case AVADDUS: /* vaddubs, vadduhs, vadduws */
			opset(AVADDUBS, r0)
			opset(AVADDUHS, r0)

	ALVXL
	ALVSL
	ALVSR
	ASTVEBX
	ASTVEHX
	ASTVEWX
	ASTVX
	ASTVXL
	AVAND
	AVANDC
	AVNAND
	AVOR
	AVORC
	AVNOR
	AVXOR
	AVEQV
	AVADDUM
	AVADDUBM
	AVADDUHM
	AVADDUWM
	AVADDUDM
	AVADDUQM
	AVADDCU
	AVADDCUQ
	AVADDCUW
	AVADDUS
	AVADDUBS
	AVADDUHS
	AVADDUWS
	AVADDSS
	AVADDSBS
	AVADDSHS
	AVADDSWS
	AVADDE
	AVADDEUQM
	AVADDECUQ

	VXOR V30, V29, V15; \
	VADDUWM V30, V31, V30; \
	VXOR V30, V29, V16; \
	VADDUWM V30, V31, V30; \
	VXOR V30, V29, V17; \
	VADDUWM V30, V31, V30; \
	VXOR V30, V29, V18; \
	VADDUWM V30, V31, V30; \
	VXOR V30, V29, V19; \
	VADDUWM V30, V31, V30; \
	VXOR V30, V29, V20; \
	VADDUWM V30, V31, V30; \
	VXOR V30, V29, V21; \
	VADDUWM V30, V31, V30; \
	VXOR V30, V29, V22; \
	VADDUWM V30, V31, V30

	VSPLTISW $8, V29
	VSPLTISW $7, V30
	PCALIGN $16
loop_vsx:
	VADDUWM V0, V4, V0
	VADDUWM V1, V5, V1
	VADDUWM V2, V6, V2
	VADDUWM V3, V7, V3

	VPERMXOR V12, V0, V21, V12
	VPERMXOR V13, V1, V21, V13
	VPERMXOR V14, V2, V21, V14
	VPERMXOR V15, V3, V21, V15

	VADDUWM V8, V12, V8
	VADDUWM V9, V13, V9
	VADDUWM V10, V14, V10
	VADDUWM V11, V15, V11

	VXOR V4, V8, V4
	VXOR V5, V9, V5