MOVV	ptr+0(FP), R4
	MOVV	val+8(FP), R5
	DBAR
	LLV	(R4), R6
	OR	R5, R6, R7
	SCV	R7, (R4)
	BEQ	R7, -4(PC)
	DBAR
	MOVV R6, ret+16(FP)
	RET

// func And64(addr *uint64, v uint64) old uint64
TEXT ·And64(SB), NOSPLIT, $0-24
	MOVV	ptr+0(FP), R4
	MOVV	val+8(FP), R5
	DBAR
	LLV	(R4), R6
	AND	R5, R6, R7
	SCV	R7, (R4)
	BEQ	R7, -4(PC)
	DBAR
	MOVV R6, ret+16(FP)
	RET

	MOVV	val+8(FP), R2

	SYNC
	LLV	(R1), R3
	OR	R2, R3, R4
	SCV	R4, (R1)
	BEQ	R4, -3(PC)
	SYNC
	MOVV	R3, ret+16(FP)
	RET

// func And64(addr *uint64, v uint64) old uint64
TEXT ·And64(SB), NOSPLIT, $0-24
	MOVV	ptr+0(FP), R1
	MOVV	val+8(FP), R2

	SYNC
	LLV	(R1), R3
	AND	R2, R3, R4
	SCV	R4, (R1)
	BEQ	R4, -3(PC)
	SYNC
	MOVV	R3, ret+16(FP)
	RET

	"MOVWR",
	"MUL",
	"MULD",
	"MULF",
	"MULU",
	"MULH",
	"MULHU",
	"MULW",
	"NEGD",
	"NEGF",
	"NEGW",
	"NEGV",
	"NOOP",
	"NOR",
	"OR",
	"REM",
	"REMU",
	"RFE",
	"SC",
	"SCV",
	"SGT",
	"SGTU",
	"SLL",
	"SQRTD",
	"SQRTF",
	"SRA",
	"SRL",
	"ROTR",
	"SUB",
	"SUBD",
	"SUBF",
	"SUBU",
	"SUBW",
	"DBAR",
	"SYSCALL",
	"TEQ",
	"TNE",
	"WORD",

	_      CacheLinePad
}

// For ppc64(le), it is safe to check only for ISA level starting on ISA v3.00,
// since there are no optional categories. There are some exceptions that also
// require kernel support to work (darn, scv), so there are feature bits for
// those as well. The minimum processor requirement is POWER8 (ISA 2.07).
// The struct is padded to avoid false sharing.
var PPC64 struct {
	_         CacheLinePad

	MOVWU	R4, 1(R5)		// a4048029
	MOVV	R4, 1(R5)		// a404c029
	MOVB	R4, 1(R5)		// a4040029
	MOVBU	R4, 1(R5)		// a4040029
	MOVWL	R4, 1(R5)		// a404002f
	MOVVL	R4, 1(R5)		// a404802f
	SC	R4, 1(R5)		// a4040021
	SCV	R4, 1(R5)		// a4040023
	MOVW	y+8(FP), R4		// 64408028
	MOVWU	y+8(FP), R4		// 6440802a
	MOVV	y+8(FP), R4		// 6440c028
	MOVB	y+8(FP), R4		// 64400028
	MOVBU	y+8(FP), R4		// 6440002a
	MOVWL	y+8(FP), R4		// 6440002e

//
// For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00,
// since there are no optional categories. There are some exceptions that also
// require kernel support to work (DARN, SCV), so there are feature bits for
// those as well. The struct is padded to avoid false sharing.
var PPC64 struct {
	_        CacheLinePad
	HasDARN  bool // Hardware random number generator (requires kernel enablement)