// ppc64le:"MOVW",-"MOVH",-"SRW"
	p.a = uint16(x)
	// amd64:-"MOVW",-"SHRL"
	// arm64:-"MOVH",-"UBFX"
	// ppc64le:-"MOVH",-"SRW"
	p.b = uint16(x >> 16)
}
func store16be(p *struct{ a, b uint16 }, x uint32) {
	// ppc64:"MOVW",-"MOVH",-"SRW"
	// s390x:"MOVW",-"MOVH",-"SRW"
	p.a = uint16(x >> 16)
	// ppc64:-"MOVH",-"SRW"
	// s390x:-"MOVH",-"SRW"
	p.b = uint16(x)
}

	c[1] = c[((v>>7)&0x3F)<<7]
}

func checkShiftMask(a uint32, b uint64, z []uint32, y []uint64) {
	_ = y[128]
	_ = z[128]
	// ppc64x: -"MOVBZ", -"SRW", "RLWNM"
	z[0] = uint32(uint8(a >> 5))
	// ppc64x: -"MOVBZ", -"SRW", "RLWNM"
	z[1] = uint32(uint8((a >> 4) & 0x7e))
	// ppc64x: "RLWNM\t[$]25, R[0-9]+, [$]27, [$]29, R[0-9]+"
	z[2] = uint32(uint8(a>>7)) & 0x1c
	// ppc64x: -"MOVWZ"

(Lsh8x(64|32|16|8)   x y) && shiftIsBounded(v) => (SLW x y)
(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRD x y)
(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW x y)
(Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) => (SRW (MOVHZreg x) y)
(Rsh8Ux(64|32|16|8)  x y) && shiftIsBounded(v) => (SRW (MOVBZreg x) y)
(Rsh64x(64|32|16|8)  x y) && shiftIsBounded(v) => (SRAD x y)
(Rsh32x(64|32|16|8)  x y) && shiftIsBounded(v) => (SRAW x y)

	"NOR",
	"NORCC",
	"OR",
	"ORCC",
	"ORN",
	"ORNCC",
	"ORIS",
	"REM",
	"REMU",
	"RFI",
	"RLWMI",
	"RLWMICC",
	"RLWNM",
	"RLWNMCC",
	"CLRLSLWI",
	"SLW",
	"SLWCC",
	"SRW",
	"SRAW",
	"SRAWCC",
	"SRWCC",
	"STBCCC",
	"STHCCC",
	"STSW",
	"STWCCC",
	"SUB",
	"SUBCC",
	"SUBVCC",
	"SUBC",
	"SUBCCC",
	"SUBCV",
	"SUBCVCC",
	"SUBME",
	"SUBMECC",

	"MOVDEQ",
	"MOVDGE",
	"MOVDGT",
	"MOVDLE",
	"MOVDLT",
	"MOVDNE",
	"LOCR",
	"LOCGR",
	"FLOGR",
	"POPCNT",
	"AND",
	"ANDW",
	"OR",
	"ORW",
	"XOR",
	"XORW",
	"SLW",
	"SLD",
	"SRW",
	"SRAW",
	"SRD",
	"SRAD",
	"RLL",
	"RLLG",
	"RNSBG",
	"RXSBG",
	"ROSBG",
	"RNSBGT",
	"RXSBGT",
	"ROSBGT",
	"RISBG",
	"RISBGN",
	"RISBGZ",
	"RISBGNZ",
	"RISBHG",
	"RISBLG",

	BR  L1
L5:
	WORD    $0xED005070 //ddb   %f0,.L15-.L10(%r5)
	BYTE    $0x00
	BYTE    $0x1D
	FMOVD   F0, ret+8(FP)
	RET

L9:
	FMOVD   F0, F2
	MOVD    $·atanhtabh2075<>+0(SB), R2
	SRW $31, R1, R1
	FMOVD   104(R5), F4
	MOVW    R1, R1
	SLD $3, R1, R1
	WORD    $0x68012000 //ld    %f0,0(%r1,%r2)
	WFMADB  V2, V4, V0, V4
	VLEG    $0, 96(R5), V16
	FDIV    F4, F2

	XORW	-1(R1), R2            // e3201fffff57

	// shift and rotate instructions
	SRD	$4, R4, R7              // eb740004000c
	SRD	R1, R4, R7              // eb741000000c
	SRW	$4, R4, R7              // eb74000400de
	SRW	R1, R4, R7              // eb74100000de
	SLW	$4, R3, R6              // eb63000400df
	SLW	R2, R3, R6              // eb63200000df
	SLD	$4, R3, R6              // eb630004000d

// or return 0 if they cannot be combined.
func mergePPC64SldiSrw(sld, srw int64) int64 {
	if sld > srw || srw >= 32 {
		return 0
	}
	mask_r := uint32(0xFFFFFFFF) >> uint(srw)
	mask_l := uint32(0xFFFFFFFF) >> uint(sld)
	mask := (mask_r & mask_l) << uint(sld)
	return encodePPC64RotateMask((32-srw+sld)&31, int64(mask), 32)
}

		v.AddArg2(x, y)
		return true
	}
	// match: (SRW x (MOVWreg y))
	// result: (SRW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVWreg {
			break
		}
		y := v_1.Args[0]
		v.reset(OpS390XSRW)
		v.AddArg2(x, y)
		return true
	}
	// match: (SRW x (MOVHreg y))
	// result: (SRW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVHreg {

	case FADDCC, FADDSCC, FSUBCC, FMULCC, FDIVCC, FDIVSCC:
		return true
	case OR, ORCC, ORC, ORCCC, AND, ANDCC, ANDC, ANDCCC, XOR, XORCC, NAND, NANDCC, EQV, EQVCC, NOR, NORCC:
		return true
	case SLW, SLWCC, SLD, SLDCC, SRW, SRAW, SRWCC, SRAWCC, SRD, SRDCC, SRAD, SRADCC:
		return true
	}
	return false
}

// revCondMap maps a conditional register bit to its inverse, if possible.
var revCondMap = map[string]string{