"SW",
	"SH",
	"SB",
	"FENCE",
	"FENCETSO",
	"PAUSE",
	"ADDIW",
	"SLLIW",
	"SRLIW",
	"SRAIW",
	"ADDW",
	"SLLW",
	"SRLW",
	"SUBW",
	"SRAW",
	"LD",
	"SD",
	"MUL",
	"MULH",
	"MULHU",
	"MULHSU",
	"MULW",
	"DIV",
	"DIVU",
	"REM",
	"REMU",
	"DIVW",
	"DIVUW",
	"REMW",
	"REMUW",
	"LRD",
	"SCD",
	"LRW",
	"SCW",
	"AMOSWAPD",
	"AMOADDD",
	"AMOANDD",
	"AMOORD",

	return uint64(v) >> 8
}

func rshConst64x64(v int64) int64 {
	// ppc64x:"SRAD"
	// riscv64:"SRAI\t",-"OR",-"SLTIU"
	return v >> uint64(33)
}

func rshConst64x64Overflow32(v int32) int64 {
	// riscv64:"SRAIW",-"SLLI",-"SRAI\t"
	return int64(v) >> 32
}

func rshConst64x64Overflow16(v int16) int64 {
	// riscv64:"SLLI","SRAI",-"SRAIW"
	return int64(v) >> 16
}

func rshConst64x64Overflow8(v int8) int64 {

(SRAI <t> [x] (MOVWreg  y)) && x >= 0 && x <= 31 => (SRAIW <t> [int64(x)] y)
(SRLI <t> [x] (MOVWUreg y)) && x >= 0 && x <= 31 => (SRLIW <t> [int64(x)] y)

// Replace right shifts that exceed size of signed type.
(SRAI <t> [x] (MOVBreg y)) && x >=  8 => (SRAI  [63] (SLLI <t> [56] y))
(SRAI <t> [x] (MOVHreg y)) && x >= 16 => (SRAI  [63] (SLLI <t> [48] y))
(SRAI <t> [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y)

	SRLW	X5, X7					// bbd35300
	SUBW	X5, X7					// bb835340
	SRAW	X5, X7					// bbd35340
	ADDW	$1, X6					// 1b031300
	SLLW	$1, X6					// 1b131300
	SRLW	$1, X6					// 1b531300
	SUBW	$1, X6					// 1b03f3ff
	SRAW	$1, X6					// 1b531340

	// 5.3: Load and Store Instructions (RV64I)
	LD	(X5), X6				// 03b30200
	LD	4(X5), X6				// 03b34200
	SD	X5, (X6)				// 23305300
	SD	X5, 4(X6)				// 23325300

	"NORCC",
	"OR",
	"ORCC",
	"ORN",
	"ORNCC",
	"ORIS",
	"REM",
	"REMU",
	"RFI",
	"RLWMI",
	"RLWMICC",
	"RLWNM",
	"RLWNMCC",
	"CLRLSLWI",
	"SLW",
	"SLWCC",
	"SRW",
	"SRAW",
	"SRAWCC",
	"SRWCC",
	"STBCCC",
	"STHCCC",
	"STSW",
	"STWCCC",
	"SUB",
	"SUBCC",
	"SUBVCC",
	"SUBC",
	"SUBCCC",
	"SUBCV",
	"SUBCVCC",
	"SUBME",
	"SUBMECC",

	"MOVDGT",
	"MOVDLE",
	"MOVDLT",
	"MOVDNE",
	"LOCR",
	"LOCGR",
	"FLOGR",
	"POPCNT",
	"AND",
	"ANDW",
	"OR",
	"ORW",
	"XOR",
	"XORW",
	"SLW",
	"SLD",
	"SRW",
	"SRAW",
	"SRD",
	"SRAD",
	"RLL",
	"RLLG",
	"RNSBG",
	"RXSBG",
	"ROSBG",
	"RNSBGT",
	"RXSBGT",
	"ROSBGT",
	"RISBG",
	"RISBGN",
	"RISBGZ",
	"RISBGNZ",
	"RISBHG",
	"RISBLG",
	"RISBHGZ",

(S(LD|RD|RAD|LW|RW|RAW) x (AND (MOVDconst [c]) y))
  => (S(LD|RD|RAD|LW|RW|RAW) x (ANDWconst <typ.UInt32> [int32(c&63)] y))
(S(LD|RD|RAD|LW|RW|RAW) x (ANDWconst [c] y)) && c&63 == 63
  => (S(LD|RD|RAD|LW|RW|RAW) x y)
(SLD  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SLD  x y)
(SRD  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRD  x y)
(SRAD x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SRAD x y)
(SLW  x (MOV(W|H|B|WZ|HZ|BZ)reg y)) => (SLW  x y)

		v.AddArg2(x, y)
		return true
	}
	// match: (SRAW x (MOVWreg y))
	// result: (SRAW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVWreg {
			break
		}
		y := v_1.Args[0]
		v.reset(OpS390XSRAW)
		v.AddArg2(x, y)
		return true
	}
	// match: (SRAW x (MOVHreg y))
	// result: (SRAW x y)
	for {
		x := v_0
		if v_1.Op != OpS390XMOVHreg {

	SRD	R1, R4, R7              // eb741000000c
	SRW	$4, R4, R7              // eb74000400de
	SRW	R1, R4, R7              // eb74100000de
	SLW	$4, R3, R6              // eb63000400df
	SLW	R2, R3, R6              // eb63200000df
	SLD	$4, R3, R6              // eb630004000d
	SLD	R2, R3, R6              // eb632000000d
	SRAD	$4, R5, R8              // eb850004000a
	SRAD	R3, R5, R8              // eb853000000a

		{name: "SRA", argLength: 2, reg: gp21, asm: "SRA"},                   // arg0 >> (aux1 & 63), arithmetic right shift
		{name: "SRAW", argLength: 2, reg: gp21, asm: "SRAW"},                 // arg0 >> (aux1 & 31), arithmetic right shift of 32 bit value, sign extended to 64 bits