VMOVDQU16 Z8, K4, (CX)                             // 6271ff4c7f01
	VMOVDQU16 Z6, K4, 99(R15)                          // 62d1ff4c7fb763000000
	VMOVDQU16 Z8, K4, 99(R15)                          // 6251ff4c7f8763000000
	VMOVDQU16 Z12, K1, Z25                             // 6211ff497fe1
	VMOVDQU16 Z17, K1, Z25                             // 6281ff497fc9
	VMOVDQU16 99(R15)(R15*2), K1, Z25                  // 6201ff496f8c7f63000000

	VANDNPD 99(R15)(R15*8), Y12, K5, Y0                // 62919d2d5584ff63000000
	VANDNPD 7(AX)(CX*8), Y12, K5, Y0                   // 62f19d2d5584c807000000
	VANDNPD Y17, Y1, K5, Y0                            // 62b1f52d55c1
	VANDNPD Y7, Y1, K5, Y0                             // 62f1f52d55c7
	VANDNPD Y9, Y1, K5, Y0                             // 62d1f52d55c1

var regNamesAMD64 = []string{
	"AX",
	"CX",
	"DX",
	"BX",
	"SP",
	"BP",
	"SI",
	"DI",
	"R8",
	"R9",
	"R10",
	"R11",
	"R12",
	"R13",
	"g", // a.k.a. R14
	"R15",
	"X0",
	"X1",
	"X2",
	"X3",
	"X4",
	"X5",
	"X6",
	"X7",
	"X8",
	"X9",
	"X10",
	"X11",
	"X12",
	"X13",
	"X14",
	"X15", // constant 0 in ABIInternal

#define itr2 R9 // general iterator
#define itr1 CX // general iterator
#define acc0 R10
#define acc1 R11
#define acc2 R12
#define t0 R13
#define t1 R14
#define t2 R15
#define t3 R8
// Register and stack allocation for the SSE code
#define rStore (0*16)(BP)
#define sStore (1*16)(BP)
#define state1Store (2*16)(BP)
#define state2Store (3*16)(BP)
#define tmpStore (4*16)(BP)

	*R12
}

type R6 R5
type R7 R5
type R8 R5

type R9 struct {
	*R13
	*R14
	*R15
	*R16
}

type R10 R9
type R11 R9
type R12 R9

type R13 struct {
	*R17
	*R18
	*R19
	*R20
}

type R14 R13
type R15 R13
type R16 R13

type R17 struct {
	*R21
	*R22
	*R23
	*R24
}

type R18 R17