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Results 21 - 30 of 63 for MOVW (0.28 sec)
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src/runtime/mkpreempt.go
} l.add("MOVW", reg, 4) } // Add flag register. l.addSpecial( "MOVW CPSR, R0\nMOVW R0, %d(R13)", "MOVW %d(R13), R0\nMOVW R0, CPSR", 4) // Add floating point registers F0-F15 and flag register. var lfp = layout{stack: l.stack, sp: "R13"} lfp.addSpecial( "MOVW FPCR, R0\nMOVW R0, %d(R13)", "MOVW %d(R13), R0\nMOVW R0, FPCR", 4)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 15.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "MOVWstorezero", argLength: 2, reg: gpstore0, aux: "SymOff", asm: "MOVW", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"}, // store 4 bytes of zero to arg0 + auxInt + aux. arg1=mem. // moves (no conversion) {name: "MOVWfpgp", argLength: 1, reg: fpgp, asm: "MOVW"}, // move float32 to int32 (no conversion) {name: "MOVWgpfp", argLength: 1, reg: gpfp, asm: "MOVW"}, // move int32 to float32 (no conversion) // conversions
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
test/codegen/shift.go
func lshConst32x64(v int32) int32 { // ppc64x:"SLW" // riscv64:"SLLI",-"AND",-"SLTIU", -"MOVW" return v << uint64(29) } func rshConst32Ux64(v uint32) uint32 { // ppc64x:"SRW" // riscv64:"SRLIW",-"AND",-"SLTIU", -"MOVW" return v >> uint64(29) } func rshConst32x64(v int32) int32 { // ppc64x:"SRAW" // riscv64:"SRAIW",-"OR",-"SLTIU", -"MOVW" return v >> uint64(29) } func lshConst64x32(v int64) int64 {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 21 18:53:43 UTC 2024 - 12.7K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
op, args = fpTrans(&inst, op, args) // LDR/STR like instructions -> MOV like switch inst.Op &^ 15 { case MOV_EQ: op = "MOVW" + op[3:] case LDR_EQ, MSR_EQ, MRS_EQ: op = "MOVW" + op[3:] + suffix case VMRS_EQ, VMSR_EQ: op = "MOVW" + op[4:] + suffix case LDRB_EQ, UXTB_EQ: op = "MOVBU" + op[4:] + suffix case LDRSB_EQ: op = "MOVBS" + op[5:] + suffix case SXTB_EQ:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "MOVWloadidx", argLength: 3, reg: gp2load, asm: "MOVW", typ: "UInt32"}, // load from arg0 + arg1. arg2=mem {name: "MOVWloadshiftLL", argLength: 3, reg: gp2load, asm: "MOVW", aux: "Int32", typ: "UInt32"}, // load from arg0 + arg1<<auxInt. arg2=mem {name: "MOVWloadshiftRL", argLength: 3, reg: gp2load, asm: "MOVW", aux: "Int32", typ: "UInt32"}, // load from arg0 + arg1>>auxInt, unsigned shift. arg2=mem
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
test/codegen/memops.go
y[16*i+1] = t // amd64: `MOVW\t[$]77, 2\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*2\)` // 386: `MOVW\t[$]77, 2\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*2\)` x[i+1] = 77 // amd64: `MOVW\t[$]77, 2\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*[12]\)` // 386: `MOVW\t[$]77, 2\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*[12]\)` x[16*i+1] = 77 } func idxInt32(x, y []int32, i int) { var t int32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 12.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
MOVD $-8589934592, R1 // c01efffffffe MOVW $-131072, R2 // c021fffe0000 MOVH $-512, R3 // a739fe00 MOVB $-1, R4 // a749ffff MOVD $32767, n-8(SP) // e548f0107fff MOVD $-1, -524288(R1) // e3a010008071e548a000ffff MOVW $32767, n-8(SP) // e54cf0107fff MOVW $-32768, 4096(R2) // e3a020000171e54ca0008000 MOVH $512, n-8(SP) // e544f0100200
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jul 24 01:11:41 UTC 2023 - 43.9K bytes - Viewed (0) -
src/math/pow_s390x.s
BYTE $0x00 BYTE $0x00 ORW R2, R1, R3 MOVW R3, R6 CMPBLT R6, $0, L43 L1: FMOVD F1, ret+16(FP) RET L43: LTDBR F0, F0 BLTU L44 FMOVD F0, F3 L7: MOVD $·pow_xinf<>+0(SB), R3 FMOVD 0(R3), F5 WFCEDBS V3, V5, V7 BVS L8 WFMDB V3, V2, V6 L8: WFCEDBS V2, V2, V3 BVS L9 LTDBR F2, F2 BEQ L26 MOVW R1, R6 CMPBLT R6, $0, L45 L11:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 16.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
MOVH (X5), X6 // 03930200 MOVH 4(X5), X6 // 03934200 MOVW (X5), X6 // 03a30200 MOVW 4(X5), X6 // 03a34200 MOV X5, (X6) // 23305300 MOV X5, 4(X6) // 23325300 MOVB X5, (X6) // 23005300 MOVB X5, 4(X6) // 23025300 MOVH X5, (X6) // 23105300 MOVH X5, 4(X6) // 23125300 MOVW X5, (X6) // 23205300 MOVW X5, 4(X6) // 23225300 MOVB X5, X6 // 1393820313538343 or 13934260
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 22 04:42:21 UTC 2024 - 16.7K bytes - Viewed (0)