MOVW R6, 28(R13)
	MOVW R7, 32(R13)
	MOVW R8, 36(R13)
	MOVW R9, 40(R13)
	MOVW R11, 44(R13)
	MOVW R12, 48(R13)
	MOVW CPSR, R0
	MOVW R0, 52(R13)
	MOVB ·goarmsoftfp(SB), R0
	CMP $0, R0
	BNE nofp
	MOVW FPCR, R0
	MOVW R0, 56(R13)
	MOVD F0, 60(R13)
	MOVD F1, 68(R13)
	MOVD F2, 76(R13)
	MOVD F3, 84(R13)
	MOVD F4, 92(R13)
	MOVD F5, 100(R13)
	MOVD F6, 108(R13)
	MOVD F7, 116(R13)
	MOVD F8, 124(R13)

		return fmt.Sprintf("R%d", r-REG_R0)
	}
	if REG_F0 <= r && r <= REG_F15 {
		return fmt.Sprintf("F%d", r-REG_F0)
	}

	switch r {
	case REG_FPSR:
		return "FPSR"

	case REG_FPCR:
		return "FPCR"

	case REG_CPSR:
		return "CPSR"

	case REG_SPSR:
		return "SPSR"

	case REG_MB_SY:
		return "MB_SY"
	case REG_MB_ST:
		return "MB_ST"
	case REG_MB_ISH:
		return "MB_ISH"

	/* FP-SIMD registers are saved in sigcontext.__reserved, which is orgnized in
	the following C structs:
	struct fpsimd_context {
		struct _aarch64_ctx head;
		__u32 fpsr;
		__u32 fpcr;
		__uint128_t vregs[32];
	};
	struct _aarch64_ctx {
		__u32 magic;
		__u32 size;
	};
	So the offset of the ith FP_SIMD register is 16+i*128.
	*/

	pc    uint64     // program counter
	cpsr  uint32     // current program status register
	__pad uint32
}

type neonstate64 struct {
	v    [64]uint64 // actually [32]uint128
	fpsr uint32
	fpcr uint32
}

type mcontext64 struct {
	es exceptionstate64
	ss regs64
	ns neonstate64
}

type ucontext struct {
	uc_onstack  int32
	uc_sigmask  uint32
	uc_stack    stackt

type context struct {
	contextflags uint32
	cpsr         uint32
	x            [31]uint64 // fp is x[29], lr is x[30]
	xsp          uint64
	pc           uint64
	v            [32]neon128
	fpcr         uint32
	fpsr         uint32
	bcr          [8]uint32
	bvr          [8]uint64
	wcr          [2]uint32
	wvr          [2]uint64
}

func (c *context) ip() uintptr { return uintptr(c.pc) }

		"MOVW %d(R13), R0\nMOVW R0, CPSR",
		4)

	// Add floating point registers F0-F15 and flag register.
	var lfp = layout{stack: l.stack, sp: "R13"}
	lfp.addSpecial(
		"MOVW FPCR, R0\nMOVW R0, %d(R13)",
		"MOVW %d(R13), R0\nMOVW R0, FPCR",
		4)
	for i := 0; i <= 15; i++ {
		reg := fmt.Sprintf("F%d", i)
		lfp.add("MOVD", reg, 8)
	}

	p("MOVW.W R14, -%d(R13)", lfp.stack) // allocate frame, save LR
	l.save()

	{"ERXSTATUS_EL1", REG_ERXSTATUS_EL1, 0x185440, SR_READ | SR_WRITE},
	{"ESR_EL1", REG_ESR_EL1, 0x185200, SR_READ | SR_WRITE},
	{"FAR_EL1", REG_FAR_EL1, 0x186000, SR_READ | SR_WRITE},
	{"FPCR", REG_FPCR, 0x1b4400, SR_READ | SR_WRITE},
	{"FPSR", REG_FPSR, 0x1b4420, SR_READ | SR_WRITE},
	{"GCR_EL1", REG_GCR_EL1, 0x1810c0, SR_READ | SR_WRITE},
	{"GMID_EL1", REG_GMID_EL1, 0x31400, SR_READ},

	MSR	R17, FAR_EL1                       // 116018d5
	MRS	FAR_EL1, R9                        // 096038d5
	MSR	R25, FAR_EL1                       // 196018d5
	MRS	FPCR, R1                           // 01443bd5
	MSR	R27, FPCR                          // 1b441bd5
	MRS	FPSR, R5                           // 25443bd5
	MSR	R15, FPSR                          // 2f441bd5
	MRS	ID_AA64AFR0_EL1, R19               // 930538d5